maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

[ARM] FP16: codegen support for VACGT 

Differential Revision: https://reviews.llvm.org/D50236

llvm-svn: 339148
This commit is contained in:
Sjoerd Meijer 2018-08-07 15:11:47 +00:00
parent 1bfadb0499
commit b39cd886b9
2 changed files with 18 additions and 28 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
llvm/lib/Target/ARM/ARMInstrNEON.td
View File

@ -5072,7 +5072,7 @@ def VACGThd : N3VDInt<1, 0, 0b11, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacgt",
"f16", v4i16, v4f16, int_arm_neon_vacgt, 0>, "f16", v4i16, v4f16, int_arm_neon_vacgt, 0>,
Requires<[HasNEON, HasFullFP16]>; Requires<[HasNEON, HasFullFP16]>;
def VACGThq : N3VQInt<1, 0, 0b11, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacgt", def VACGThq : N3VQInt<1, 0, 0b11, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacgt",
"f16", v8f16, v8f16, int_arm_neon_vacgt, 0>, "f16", v8i16, v8f16, int_arm_neon_vacgt, 0>,
Requires<[HasNEON, HasFullFP16]>; Requires<[HasNEON, HasFullFP16]>;
// VTST : Vector Test Bits // VTST : Vector Test Bits
defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,

44
llvm/test/CodeGen/ARM/armv8.2a-fp16-vector-intrinsics.ll
View File

@ -522,19 +522,23 @@ entry:
ret <8 x i16> %vcageq_v2.i ret <8 x i16> %vcageq_v2.i
} }
; FIXME (PR38404) define dso_local <4 x i16> @test_vcagt_f16(<4 x half> %a, <4 x half> %b) {
; ; CHECK-LABEL: test_vcagt_f16:
;define dso_local <4 x i16> @test_vcagt_f16(<4 x half> %a, <4 x half> %b) { ; CHECK: vacgt.f16 d0, d0, d1
;entry: ; CHECK-NEXT: bx lr
; %vcagt_v2.i = tail call <4 x i16> @llvm.arm.neon.vacgt.v4i16.v4f16(<4 x half> %a, <4 x half> %b) entry:
; ret <4 x i16> %vcagt_v2.i %vcagt_v2.i = tail call <4 x i16> @llvm.arm.neon.vacgt.v4i16.v4f16(<4 x half> %a, <4 x half> %b)
;} ret <4 x i16> %vcagt_v2.i
; }
;define dso_local <8 x i16> @test_vcagtq_f16(<8 x half> %a, <8 x half> %b) {
;entry: define dso_local <8 x i16> @test_vcagtq_f16(<8 x half> %a, <8 x half> %b) {
; %vcagtq_v2.i = tail call <8 x i16> @llvm.arm.neon.vacgt.v8i16.v8f16(<8 x half> %a, <8 x half> %b) ; CHECK-LABEL: test_vcagtq_f16:
; ret <8 x i16> %vcagtq_v2.i ; CHECK: vacgt.f16 q0, q0, q1
;} ; CHECK-NEXT: bx lr
entry:
%vcagtq_v2.i = tail call <8 x i16> @llvm.arm.neon.vacgt.v8i16.v8f16(<8 x half> %a, <8 x half> %b)
ret <8 x i16> %vcagtq_v2.i
}
define dso_local <4 x i16> @test_vcale_f16(<4 x half> %a, <4 x half> %b) { define dso_local <4 x i16> @test_vcale_f16(<4 x half> %a, <4 x half> %b) {
; CHECKLABEL: test_vcale_f16: ; CHECKLABEL: test_vcale_f16:
@ -554,20 +558,6 @@ entry:
ret <8 x i16> %vcaleq_v2.i ret <8 x i16> %vcaleq_v2.i
} }
; FIXME (PR38404)
;
;define dso_local <4 x i16> @test_vcalt_f16(<4 x half> %a, <4 x half> %b) {
;entry:
; %vcalt_v2.i = tail call <4 x i16> @llvm.arm.neon.vacgt.v4i16.v4f16(<4 x half> %b, <4 x half> %a)
; ret <4 x i16> %vcalt_v2.i
;}
;define dso_local <8 x i16> @test_vcaltq_f16(<8 x half> %a, <8 x half> %b) {
;entry:
; %vcaltq_v2.i = tail call <8 x i16> @llvm.arm.neon.vacgt.v8i16.v8f16(<8 x half> %b, <8 x half> %a)
; ret <8 x i16> %vcaltq_v2.i
;}
define dso_local <4 x i16> @test_vceq_f16(<4 x half> %a, <4 x half> %b) { define dso_local <4 x i16> @test_vceq_f16(<4 x half> %a, <4 x half> %b) {
; CHECKLABEL: test_vceq_f16: ; CHECKLABEL: test_vceq_f16:
; CHECK: vceq.f16 d0, d0, d1 ; CHECK: vceq.f16 d0, d0, d1