forked from OSchip/llvm-project
Add useAA() to TargetSubtargetInfo
There are several optional (off-by-default) features in CodeGen that can make use of alias analysis. These features are important for generating code for some kinds of cores (for example the (in-order) PPC A2 core). This adds a useAA() function to TargetSubtargetInfo to allow these features to be enabled by default on a per-subtarget basis. Here is the first use of this function: To control the default of the -enable-aa-sched-mi feature. llvm-svn: 189563
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@ -75,6 +75,10 @@ public:
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virtual void adjustSchedDependency(SUnit *def, SUnit *use,
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SDep& dep) const { }
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/// \brief Enable use of alias analysis during code generation (during MI
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/// scheduling, DAGCombine, etc.).
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virtual bool useAA() const;
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/// \brief Reset the features for the subtarget.
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virtual void resetSubtargetFeatures(const MachineFunction *MF) { }
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};
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@ -640,8 +640,7 @@ void addChainDependency (AliasAnalysis *AA, const MachineFrameInfo *MFI,
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bool isNormalMemory = false) {
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// If this is a false dependency,
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// do not add the edge, but rememeber the rejected node.
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if (!EnableAASchedMI ||
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MIsNeedChainEdge(AA, MFI, SUa->getInstr(), SUb->getInstr())) {
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if (!AA || MIsNeedChainEdge(AA, MFI, SUa->getInstr(), SUb->getInstr())) {
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SDep Dep(SUa, isNormalMemory ? SDep::MayAliasMem : SDep::Barrier);
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Dep.setLatency(TrueMemOrderLatency);
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SUb->addPred(Dep);
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@ -692,6 +691,11 @@ void ScheduleDAGInstrs::initSUnits() {
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/// operands.
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void ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA,
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RegPressureTracker *RPTracker) {
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const TargetSubtargetInfo &ST = TM.getSubtarget<TargetSubtargetInfo>();
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bool UseAA = EnableAASchedMI.getNumOccurrences() > 0 ? EnableAASchedMI
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: ST.useAA();
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AliasAnalysis *AAForDep = UseAA ? AA : 0;
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// Create an SUnit for each real instruction.
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initSUnits();
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@ -830,20 +834,20 @@ void ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA,
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unsigned ChainLatency = 0;
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if (AliasChain->getInstr()->mayLoad())
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ChainLatency = TrueMemOrderLatency;
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addChainDependency(AA, MFI, SU, AliasChain, RejectMemNodes,
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addChainDependency(AAForDep, MFI, SU, AliasChain, RejectMemNodes,
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ChainLatency);
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}
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AliasChain = SU;
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for (unsigned k = 0, m = PendingLoads.size(); k != m; ++k)
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addChainDependency(AA, MFI, SU, PendingLoads[k], RejectMemNodes,
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addChainDependency(AAForDep, MFI, SU, PendingLoads[k], RejectMemNodes,
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TrueMemOrderLatency);
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for (MapVector<const Value *, SUnit *>::iterator I = AliasMemDefs.begin(),
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E = AliasMemDefs.end(); I != E; ++I)
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addChainDependency(AA, MFI, SU, I->second, RejectMemNodes);
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addChainDependency(AAForDep, MFI, SU, I->second, RejectMemNodes);
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for (MapVector<const Value *, std::vector<SUnit *> >::iterator I =
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AliasMemUses.begin(), E = AliasMemUses.end(); I != E; ++I) {
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for (unsigned i = 0, e = I->second.size(); i != e; ++i)
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addChainDependency(AA, MFI, SU, I->second[i], RejectMemNodes,
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addChainDependency(AAForDep, MFI, SU, I->second[i], RejectMemNodes,
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TrueMemOrderLatency);
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}
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adjustChainDeps(AA, MFI, SU, &ExitSU, RejectMemNodes,
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@ -876,7 +880,8 @@ void ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA,
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MapVector<const Value *, SUnit *>::iterator IE =
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((ThisMayAlias) ? AliasMemDefs.end() : NonAliasMemDefs.end());
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if (I != IE) {
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addChainDependency(AA, MFI, SU, I->second, RejectMemNodes, 0, true);
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addChainDependency(AAForDep, MFI, SU, I->second, RejectMemNodes,
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0, true);
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I->second = SU;
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} else {
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if (ThisMayAlias)
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@ -891,7 +896,7 @@ void ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA,
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((ThisMayAlias) ? AliasMemUses.end() : NonAliasMemUses.end());
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if (J != JE) {
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for (unsigned i = 0, e = J->second.size(); i != e; ++i)
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addChainDependency(AA, MFI, SU, J->second[i], RejectMemNodes,
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addChainDependency(AAForDep, MFI, SU, J->second[i], RejectMemNodes,
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TrueMemOrderLatency, true);
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J->second.clear();
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}
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@ -900,11 +905,11 @@ void ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA,
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// Add dependencies from all the PendingLoads, i.e. loads
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// with no underlying object.
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for (unsigned k = 0, m = PendingLoads.size(); k != m; ++k)
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addChainDependency(AA, MFI, SU, PendingLoads[k], RejectMemNodes,
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addChainDependency(AAForDep, MFI, SU, PendingLoads[k], RejectMemNodes,
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TrueMemOrderLatency);
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// Add dependence on alias chain, if needed.
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if (AliasChain)
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addChainDependency(AA, MFI, SU, AliasChain, RejectMemNodes);
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addChainDependency(AAForDep, MFI, SU, AliasChain, RejectMemNodes);
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// But we also should check dependent instructions for the
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// SU in question.
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adjustChainDeps(AA, MFI, SU, &ExitSU, RejectMemNodes,
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@ -934,7 +939,7 @@ void ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA,
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// potentially aliasing stores.
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for (MapVector<const Value *, SUnit *>::iterator I =
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AliasMemDefs.begin(), E = AliasMemDefs.end(); I != E; ++I)
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addChainDependency(AA, MFI, SU, I->second, RejectMemNodes);
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addChainDependency(AAForDep, MFI, SU, I->second, RejectMemNodes);
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PendingLoads.push_back(SU);
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MayAlias = true;
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@ -956,7 +961,8 @@ void ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA,
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MapVector<const Value *, SUnit *>::iterator IE =
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((ThisMayAlias) ? AliasMemDefs.end() : NonAliasMemDefs.end());
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if (I != IE)
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addChainDependency(AA, MFI, SU, I->second, RejectMemNodes, 0, true);
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addChainDependency(AAForDep, MFI, SU, I->second, RejectMemNodes,
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0, true);
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if (ThisMayAlias)
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AliasMemUses[V].push_back(SU);
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else
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@ -966,7 +972,7 @@ void ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA,
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adjustChainDeps(AA, MFI, SU, &ExitSU, RejectMemNodes, /*Latency=*/0);
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// Add dependencies on alias and barrier chains, if needed.
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if (MayAlias && AliasChain)
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addChainDependency(AA, MFI, SU, AliasChain, RejectMemNodes);
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addChainDependency(AAForDep, MFI, SU, AliasChain, RejectMemNodes);
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if (BarrierChain)
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BarrierChain->addPred(SDep(SU, SDep::Barrier));
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}
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@ -35,3 +35,7 @@ bool TargetSubtargetInfo::enablePostRAScheduler(
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return false;
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}
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bool TargetSubtargetInfo::useAA() const {
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return false;
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}
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