From b35022121d5d82705fd576b846eea6be9e98c0fd Mon Sep 17 00:00:00 2001 From: Diana Picus Date: Wed, 25 Oct 2017 11:42:40 +0000 Subject: [PATCH] [ARM GlobalISel] Fix call opcodes We were generating BLX for all the calls, which was incorrect in most cases. Update ARMCallLowering to generate BL for direct calls, and BLX, BX_CALL or BMOVPCRX_CALL for indirect calls. llvm-svn: 316570 --- llvm/lib/Target/ARM/ARMCallLowering.cpp | 15 +- .../ARM/GlobalISel/arm-call-lowering.ll | 16 +- .../CodeGen/ARM/GlobalISel/arm-isel-divmod.ll | 48 +++--- .../CodeGen/ARM/GlobalISel/arm-isel-fp.ll | 28 ++-- llvm/test/CodeGen/ARM/GlobalISel/arm-isel.ll | 4 +- .../ARM/GlobalISel/arm-legalize-divmod.mir | 48 +++--- .../ARM/GlobalISel/arm-legalize-fp.mir | 152 +++++++++--------- .../ARM/GlobalISel/arm-param-lowering.ll | 26 +-- 8 files changed, 174 insertions(+), 163 deletions(-) diff --git a/llvm/lib/Target/ARM/ARMCallLowering.cpp b/llvm/lib/Target/ARM/ARMCallLowering.cpp index bfa0d9f7c301..e1323cd9427e 100644 --- a/llvm/lib/Target/ARM/ARMCallLowering.cpp +++ b/llvm/lib/Target/ARM/ARMCallLowering.cpp @@ -493,19 +493,26 @@ bool ARMCallLowering::lowerCall(MachineIRBuilder &MIRBuilder, MachineFunction &MF = MIRBuilder.getMF(); const auto &TLI = *getTLI(); const auto &DL = MF.getDataLayout(); - const auto &STI = MF.getSubtarget(); + const auto &STI = MF.getSubtarget(); const TargetRegisterInfo *TRI = STI.getRegisterInfo(); MachineRegisterInfo &MRI = MF.getRegInfo(); - if (MF.getSubtarget().genLongCalls()) + if (STI.genLongCalls()) return false; auto CallSeqStart = MIRBuilder.buildInstr(ARM::ADJCALLSTACKDOWN); // Create the call instruction so we can add the implicit uses of arg // registers, but don't insert it yet. - auto MIB = MIRBuilder.buildInstrNoInsert(ARM::BLX).add(Callee).addRegMask( - TRI->getCallPreservedMask(MF, CallConv)); + bool isDirect = !Callee.isReg(); + auto CallOpcode = + isDirect ? ARM::BL + : STI.hasV5TOps() + ? ARM::BLX + : STI.hasV4TOps() ? ARM::BX_CALL : ARM::BMOVPCRX_CALL; + auto MIB = MIRBuilder.buildInstrNoInsert(CallOpcode) + .add(Callee) + .addRegMask(TRI->getCallPreservedMask(MF, CallConv)); if (Callee.isReg()) { auto CalleeReg = Callee.getReg(); if (CalleeReg && !TRI->isPhysicalRegister(CalleeReg)) diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-call-lowering.ll b/llvm/test/CodeGen/ARM/GlobalISel/arm-call-lowering.ll index 8e11a365b5ff..c1dd9276ddd8 100644 --- a/llvm/test/CodeGen/ARM/GlobalISel/arm-call-lowering.ll +++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-call-lowering.ll @@ -1,12 +1,16 @@ -; RUN: llc -mtriple arm-unknown -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=CHECK +; RUN: llc -mtriple arm-unknown -mattr=-v4t -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,NOV4T +; RUN: llc -mtriple arm-unknown -mattr=+v4t -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,V4T +; RUN: llc -mtriple arm-unknown -mattr=+v5t -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,V5T define arm_aapcscc void @test_indirect_call(void() *%fptr) { ; CHECK-LABEL: name: test_indirect_call -; CHECK: registers: -; CHECK-NEXT: id: [[FPTR:[0-9]+]], class: gpr -; CHECK: %[[FPTR]]:gpr(p0) = COPY %r0 +; V5T: %[[FPTR:[0-9]+]]:gpr(p0) = COPY %r0 +; V4T: %[[FPTR:[0-9]+]]:tgpr(p0) = COPY %r0 +; NOV4T: %[[FPTR:[0-9]+]]:tgpr(p0) = COPY %r0 ; CHECK: ADJCALLSTACKDOWN 0, 0, 14, _, implicit-def %sp, implicit %sp -; CHECK: BLX %[[FPTR]](p0), csr_aapcs, implicit-def %lr, implicit %sp +; V5T: BLX %[[FPTR]](p0), csr_aapcs, implicit-def %lr, implicit %sp +; V4T: BX_CALL %[[FPTR]](p0), csr_aapcs, implicit-def %lr, implicit %sp +; NOV4T: BMOVPCRX_CALL %[[FPTR]](p0), csr_aapcs, implicit-def %lr, implicit %sp ; CHECK: ADJCALLSTACKUP 0, 0, 14, _, implicit-def %sp, implicit %sp entry: notail call arm_aapcscc void %fptr() @@ -18,7 +22,7 @@ declare arm_aapcscc void @call_target() define arm_aapcscc void @test_direct_call() { ; CHECK-LABEL: name: test_direct_call ; CHECK: ADJCALLSTACKDOWN 0, 0, 14, _, implicit-def %sp, implicit %sp -; CHECK: BLX @call_target, csr_aapcs, implicit-def %lr, implicit %sp +; CHECK: BL @call_target, csr_aapcs, implicit-def %lr, implicit %sp ; CHECK: ADJCALLSTACKUP 0, 0, 14, _, implicit-def %sp, implicit %sp entry: notail call arm_aapcscc void @call_target() diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-isel-divmod.ll b/llvm/test/CodeGen/ARM/GlobalISel/arm-isel-divmod.ll index c645408d7961..5d83adeb42a8 100644 --- a/llvm/test/CodeGen/ARM/GlobalISel/arm-isel-divmod.ll +++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-isel-divmod.ll @@ -6,8 +6,8 @@ define arm_aapcscc i32 @test_sdiv_i32(i32 %a, i32 %b) { ; CHECK-LABEL: test_sdiv_i32: ; HWDIV: sdiv -; SOFT-AEABI: blx __aeabi_idiv -; SOFT-DEFAULT: blx __divsi3 +; SOFT-AEABI: bl __aeabi_idiv +; SOFT-DEFAULT: bl __divsi3 %r = sdiv i32 %a, %b ret i32 %r } @@ -15,8 +15,8 @@ define arm_aapcscc i32 @test_sdiv_i32(i32 %a, i32 %b) { define arm_aapcscc i32 @test_udiv_i32(i32 %a, i32 %b) { ; CHECK-LABEL: test_udiv_i32: ; HWDIV: udiv -; SOFT-AEABI: blx __aeabi_uidiv -; SOFT-DEFAULT: blx __udivsi3 +; SOFT-AEABI: bl __aeabi_uidiv +; SOFT-DEFAULT: bl __udivsi3 %r = udiv i32 %a, %b ret i32 %r } @@ -24,8 +24,8 @@ define arm_aapcscc i32 @test_udiv_i32(i32 %a, i32 %b) { define arm_aapcscc i16 @test_sdiv_i16(i16 %a, i16 %b) { ; CHECK-LABEL: test_sdiv_i16: ; HWDIV: sdiv -; SOFT-AEABI: blx __aeabi_idiv -; SOFT-DEFAULT: blx __divsi3 +; SOFT-AEABI: bl __aeabi_idiv +; SOFT-DEFAULT: bl __divsi3 %r = sdiv i16 %a, %b ret i16 %r } @@ -33,8 +33,8 @@ define arm_aapcscc i16 @test_sdiv_i16(i16 %a, i16 %b) { define arm_aapcscc i16 @test_udiv_i16(i16 %a, i16 %b) { ; CHECK-LABEL: test_udiv_i16: ; HWDIV: udiv -; SOFT-AEABI: blx __aeabi_uidiv -; SOFT-DEFAULT: blx __udivsi3 +; SOFT-AEABI: bl __aeabi_uidiv +; SOFT-DEFAULT: bl __udivsi3 %r = udiv i16 %a, %b ret i16 %r } @@ -42,8 +42,8 @@ define arm_aapcscc i16 @test_udiv_i16(i16 %a, i16 %b) { define arm_aapcscc i8 @test_sdiv_i8(i8 %a, i8 %b) { ; CHECK-LABEL: test_sdiv_i8: ; HWDIV: sdiv -; SOFT-AEABI: blx __aeabi_idiv -; SOFT-DEFAULT: blx __divsi3 +; SOFT-AEABI: bl __aeabi_idiv +; SOFT-DEFAULT: bl __divsi3 %r = sdiv i8 %a, %b ret i8 %r } @@ -51,8 +51,8 @@ define arm_aapcscc i8 @test_sdiv_i8(i8 %a, i8 %b) { define arm_aapcscc i8 @test_udiv_i8(i8 %a, i8 %b) { ; CHECK-LABEL: test_udiv_i8: ; HWDIV: udiv -; SOFT-AEABI: blx __aeabi_uidiv -; SOFT-DEFAULT: blx __udivsi3 +; SOFT-AEABI: bl __aeabi_uidiv +; SOFT-DEFAULT: bl __udivsi3 %r = udiv i8 %a, %b ret i8 %r } @@ -60,8 +60,8 @@ define arm_aapcscc i8 @test_udiv_i8(i8 %a, i8 %b) { define arm_aapcscc i32 @test_srem_i32(i32 %x, i32 %y) { ; CHECK-LABEL: test_srem_i32: ; HWDIV: sdiv -; SOFT-AEABI: blx __aeabi_idivmod -; SOFT-DEFAULT: blx __modsi3 +; SOFT-AEABI: bl __aeabi_idivmod +; SOFT-DEFAULT: bl __modsi3 %r = srem i32 %x, %y ret i32 %r } @@ -69,8 +69,8 @@ define arm_aapcscc i32 @test_srem_i32(i32 %x, i32 %y) { define arm_aapcscc i32 @test_urem_i32(i32 %x, i32 %y) { ; CHECK-LABEL: test_urem_i32: ; HWDIV: udiv -; SOFT-AEABI: blx __aeabi_uidivmod -; SOFT-DEFAULT: blx __umodsi3 +; SOFT-AEABI: bl __aeabi_uidivmod +; SOFT-DEFAULT: bl __umodsi3 %r = urem i32 %x, %y ret i32 %r } @@ -78,8 +78,8 @@ define arm_aapcscc i32 @test_urem_i32(i32 %x, i32 %y) { define arm_aapcscc i16 @test_srem_i16(i16 %x, i16 %y) { ; CHECK-LABEL: test_srem_i16: ; HWDIV: sdiv -; SOFT-AEABI: blx __aeabi_idivmod -; SOFT-DEFAULT: blx __modsi3 +; SOFT-AEABI: bl __aeabi_idivmod +; SOFT-DEFAULT: bl __modsi3 %r = srem i16 %x, %y ret i16 %r } @@ -87,8 +87,8 @@ define arm_aapcscc i16 @test_srem_i16(i16 %x, i16 %y) { define arm_aapcscc i16 @test_urem_i16(i16 %x, i16 %y) { ; CHECK-LABEL: test_urem_i16: ; HWDIV: udiv -; SOFT-AEABI: blx __aeabi_uidivmod -; SOFT-DEFAULT: blx __umodsi3 +; SOFT-AEABI: bl __aeabi_uidivmod +; SOFT-DEFAULT: bl __umodsi3 %r = urem i16 %x, %y ret i16 %r } @@ -96,8 +96,8 @@ define arm_aapcscc i16 @test_urem_i16(i16 %x, i16 %y) { define arm_aapcscc i8 @test_srem_i8(i8 %x, i8 %y) { ; CHECK-LABEL: test_srem_i8: ; HWDIV: sdiv -; SOFT-AEABI: blx __aeabi_idivmod -; SOFT-DEFAULT: blx __modsi3 +; SOFT-AEABI: bl __aeabi_idivmod +; SOFT-DEFAULT: bl __modsi3 %r = srem i8 %x, %y ret i8 %r } @@ -105,8 +105,8 @@ define arm_aapcscc i8 @test_srem_i8(i8 %x, i8 %y) { define arm_aapcscc i8 @test_urem_i8(i8 %x, i8 %y) { ; CHECK-LABEL: test_urem_i8: ; HWDIV: udiv -; SOFT-AEABI: blx __aeabi_uidivmod -; SOFT-DEFAULT: blx __umodsi3 +; SOFT-AEABI: bl __aeabi_uidivmod +; SOFT-DEFAULT: bl __umodsi3 %r = urem i8 %x, %y ret i8 %r } diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-isel-fp.ll b/llvm/test/CodeGen/ARM/GlobalISel/arm-isel-fp.ll index 98b39e444ac7..3fd3de2db867 100644 --- a/llvm/test/CodeGen/ARM/GlobalISel/arm-isel-fp.ll +++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-isel-fp.ll @@ -4,14 +4,14 @@ define arm_aapcscc float @test_frem_float(float %x, float %y) { ; CHECK-LABEL: test_frem_float: -; CHECK: blx fmodf +; CHECK: bl fmodf %r = frem float %x, %y ret float %r } define arm_aapcscc double @test_frem_double(double %x, double %y) { ; CHECK-LABEL: test_frem_double: -; CHECK: blx fmod +; CHECK: bl fmod %r = frem double %x, %y ret double %r } @@ -19,7 +19,7 @@ define arm_aapcscc double @test_frem_double(double %x, double %y) { declare float @llvm.pow.f32(float %x, float %y) define arm_aapcscc float @test_fpow_float(float %x, float %y) { ; CHECK-LABEL: test_fpow_float: -; CHECK: blx powf +; CHECK: bl powf %r = call float @llvm.pow.f32(float %x, float %y) ret float %r } @@ -27,7 +27,7 @@ define arm_aapcscc float @test_fpow_float(float %x, float %y) { declare double @llvm.pow.f64(double %x, double %y) define arm_aapcscc double @test_fpow_double(double %x, double %y) { ; CHECK-LABEL: test_fpow_double: -; CHECK: blx pow +; CHECK: bl pow %r = call double @llvm.pow.f64(double %x, double %y) ret double %r } @@ -35,8 +35,8 @@ define arm_aapcscc double @test_fpow_double(double %x, double %y) { define arm_aapcscc float @test_add_float(float %x, float %y) { ; CHECK-LABEL: test_add_float: ; HARD: vadd.f32 -; SOFT-AEABI: blx __aeabi_fadd -; SOFT-DEFAULT: blx __addsf3 +; SOFT-AEABI: bl __aeabi_fadd +; SOFT-DEFAULT: bl __addsf3 %r = fadd float %x, %y ret float %r } @@ -44,8 +44,8 @@ define arm_aapcscc float @test_add_float(float %x, float %y) { define arm_aapcscc double @test_add_double(double %x, double %y) { ; CHECK-LABEL: test_add_double: ; HARD: vadd.f64 -; SOFT-AEABI: blx __aeabi_dadd -; SOFT-DEFAULT: blx __adddf3 +; SOFT-AEABI: bl __aeabi_dadd +; SOFT-DEFAULT: bl __adddf3 %r = fadd double %x, %y ret double %r } @@ -55,8 +55,8 @@ define arm_aapcs_vfpcc i32 @test_cmp_float_ogt(float %x, float %y) { ; HARD: vcmp.f32 ; HARD: vmrs APSR_nzcv, fpscr ; HARD-NEXT: movgt -; SOFT-AEABI: blx __aeabi_fcmpgt -; SOFT-DEFAULT: blx __gtsf2 +; SOFT-AEABI: bl __aeabi_fcmpgt +; SOFT-DEFAULT: bl __gtsf2 entry: %v = fcmp ogt float %x, %y %r = zext i1 %v to i32 @@ -70,10 +70,10 @@ define arm_aapcs_vfpcc i32 @test_cmp_float_one(float %x, float %y) { ; HARD: movgt ; HARD-NOT: vcmp ; HARD: movmi -; SOFT-AEABI-DAG: blx __aeabi_fcmpgt -; SOFT-AEABI-DAG: blx __aeabi_fcmplt -; SOFT-DEFAULT-DAG: blx __gtsf2 -; SOFT-DEFAULT-DAG: blx __ltsf2 +; SOFT-AEABI-DAG: bl __aeabi_fcmpgt +; SOFT-AEABI-DAG: bl __aeabi_fcmplt +; SOFT-DEFAULT-DAG: bl __gtsf2 +; SOFT-DEFAULT-DAG: bl __ltsf2 entry: %v = fcmp one float %x, %y %r = zext i1 %v to i32 diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-isel.ll b/llvm/test/CodeGen/ARM/GlobalISel/arm-isel.ll index 9e3a711dea6d..3582122ba057 100644 --- a/llvm/test/CodeGen/ARM/GlobalISel/arm-isel.ll +++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-isel.ll @@ -439,9 +439,9 @@ define arm_aapcscc void @test_brcond(i32 %n) { ; CHECK-NEXT: movgt [[RCMP:r[0-9]+]], #1 ; CHECK: tst [[RCMP]], #1 ; CHECK-NEXT: bne [[FALSE:.L[[:alnum:]_]+]] -; CHECK: blx brcond1 +; CHECK: bl brcond1 ; CHECK: [[FALSE]]: -; CHECK: blx brcond2 +; CHECK: bl brcond2 entry: %cmp = icmp sgt i32 %n, 0 br i1 %cmp, label %if.true, label %if.false diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir index 5fee943423ed..996f5406b160 100644 --- a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir +++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir @@ -46,9 +46,9 @@ body: | ; SOFT: ADJCALLSTACKDOWN ; SOFT-DAG: %r0 = COPY [[X]] ; SOFT-DAG: %r1 = COPY [[Y]] - ; SOFT-AEABI: BLX $__aeabi_idiv, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-AEABI: BL $__aeabi_idiv, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = COPY %r0 - ; SOFT-DEFAULT: BLX $__divsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: BL $__divsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s32) = COPY %r0 ; SOFT: ADJCALLSTACKUP ; SOFT-NOT: G_SDIV @@ -82,9 +82,9 @@ body: | ; SOFT: ADJCALLSTACKDOWN ; SOFT-DAG: %r0 = COPY [[X]] ; SOFT-DAG: %r1 = COPY [[Y]] - ; SOFT-AEABI: BLX $__aeabi_uidiv, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-AEABI: BL $__aeabi_uidiv, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = COPY %r0 - ; SOFT-DEFAULT: BLX $__udivsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: BL $__udivsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s32) = COPY %r0 ; SOFT: ADJCALLSTACKUP ; SOFT-NOT: G_UDIV @@ -133,9 +133,9 @@ body: | ; SOFT: ADJCALLSTACKDOWN ; SOFT-DAG: %r0 = COPY [[X32]] ; SOFT-DAG: %r1 = COPY [[Y32]] - ; SOFT-AEABI: BLX $__aeabi_idiv, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-AEABI: BL $__aeabi_idiv, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY %r0 - ; SOFT-DEFAULT: BLX $__divsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: BL $__divsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY %r0 ; SOFT: ADJCALLSTACKUP ; SOFT-NOT: G_SDIV @@ -186,9 +186,9 @@ body: | ; SOFT: ADJCALLSTACKDOWN ; SOFT-DAG: %r0 = COPY [[X32]] ; SOFT-DAG: %r1 = COPY [[Y32]] - ; SOFT-AEABI: BLX $__aeabi_uidiv, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-AEABI: BL $__aeabi_uidiv, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY %r0 - ; SOFT-DEFAULT: BLX $__udivsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: BL $__udivsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY %r0 ; SOFT: ADJCALLSTACKUP ; SOFT-NOT: G_UDIV @@ -241,9 +241,9 @@ body: | ; SOFT: ADJCALLSTACKDOWN ; SOFT-DAG: %r0 = COPY [[X32]] ; SOFT-DAG: %r1 = COPY [[Y32]] - ; SOFT-AEABI: BLX $__aeabi_idiv, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-AEABI: BL $__aeabi_idiv, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY %r0 - ; SOFT-DEFAULT: BLX $__divsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: BL $__divsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY %r0 ; SOFT: ADJCALLSTACKUP ; SOFT-NOT: G_SDIV @@ -294,9 +294,9 @@ body: | ; SOFT: ADJCALLSTACKDOWN ; SOFT-DAG: %r0 = COPY [[X32]] ; SOFT-DAG: %r1 = COPY [[Y32]] - ; SOFT-AEABI: BLX $__aeabi_uidiv, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-AEABI: BL $__aeabi_uidiv, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY %r0 - ; SOFT-DEFAULT: BLX $__udivsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: BL $__udivsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY %r0 ; SOFT: ADJCALLSTACKUP ; SOFT-NOT: G_UDIV @@ -336,9 +336,9 @@ body: | ; SOFT: ADJCALLSTACKDOWN ; SOFT-DAG: %r0 = COPY [[X]] ; SOFT-DAG: %r1 = COPY [[Y]] - ; SOFT-AEABI: BLX $__aeabi_idivmod, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0, implicit-def %r1 + ; SOFT-AEABI: BL $__aeabi_idivmod, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0, implicit-def %r1 ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = COPY %r1 - ; SOFT-DEFAULT: BLX $__modsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: BL $__modsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s32) = COPY %r0 ; SOFT: ADJCALLSTACKUP ; SOFT-NOT: G_SREM @@ -374,9 +374,9 @@ body: | ; SOFT: ADJCALLSTACKDOWN ; SOFT-DAG: %r0 = COPY [[X]] ; SOFT-DAG: %r1 = COPY [[Y]] - ; SOFT-AEABI: BLX $__aeabi_uidivmod, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0, implicit-def %r1 + ; SOFT-AEABI: BL $__aeabi_uidivmod, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0, implicit-def %r1 ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = COPY %r1 - ; SOFT-DEFAULT: BLX $__umodsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: BL $__umodsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s32) = COPY %r0 ; SOFT: ADJCALLSTACKUP ; SOFT-NOT: G_UREM @@ -427,9 +427,9 @@ body: | ; SOFT: ADJCALLSTACKDOWN ; SOFT-DAG: %r0 = COPY [[X32]] ; SOFT-DAG: %r1 = COPY [[Y32]] - ; SOFT-AEABI: BLX $__aeabi_idivmod, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-AEABI: BL $__aeabi_idivmod, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY %r1 - ; SOFT-DEFAULT: BLX $__modsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: BL $__modsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY %r0 ; SOFT: ADJCALLSTACKUP ; SOFT-NOT: G_SREM @@ -482,9 +482,9 @@ body: | ; SOFT: ADJCALLSTACKDOWN ; SOFT-DAG: %r0 = COPY [[X32]] ; SOFT-DAG: %r1 = COPY [[Y32]] - ; SOFT-AEABI: BLX $__aeabi_uidivmod, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-AEABI: BL $__aeabi_uidivmod, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY %r1 - ; SOFT-DEFAULT: BLX $__umodsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: BL $__umodsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY %r0 ; SOFT: ADJCALLSTACKUP ; SOFT-NOT: G_UREM @@ -539,9 +539,9 @@ body: | ; SOFT: ADJCALLSTACKDOWN ; SOFT-DAG: %r0 = COPY [[X32]] ; SOFT-DAG: %r1 = COPY [[Y32]] - ; SOFT-AEABI: BLX $__aeabi_idivmod, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-AEABI: BL $__aeabi_idivmod, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY %r1 - ; SOFT-DEFAULT: BLX $__modsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: BL $__modsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY %r0 ; SOFT: ADJCALLSTACKUP ; SOFT-NOT: G_SREM @@ -594,9 +594,9 @@ body: | ; SOFT: ADJCALLSTACKDOWN ; SOFT-DAG: %r0 = COPY [[X32]] ; SOFT-DAG: %r1 = COPY [[Y32]] - ; SOFT-AEABI: BLX $__aeabi_uidivmod, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-AEABI: BL $__aeabi_uidivmod, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY %r1 - ; SOFT-DEFAULT: BLX $__umodsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: BL $__umodsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY %r0 ; SOFT: ADJCALLSTACKUP ; SOFT-NOT: G_UREM diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir index d3ee16390337..bdb064a9c18d 100644 --- a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir +++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir @@ -75,8 +75,8 @@ body: | ; SOFT-DAG: %r1 = COPY [[Y]] ; HARD-DAG: %s0 = COPY [[X]] ; HARD-DAG: %s1 = COPY [[Y]] - ; SOFT: BLX $fmodf, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; HARD: BLX $fmodf, {{.*}}, implicit %s0, implicit %s1, implicit-def %s0 + ; SOFT: BL $fmodf, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; HARD: BL $fmodf, {{.*}}, implicit %s0, implicit %s1, implicit-def %s0 ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY %r0 ; HARD: [[R:%[0-9]+]]:_(s32) = COPY %s0 ; CHECK: ADJCALLSTACKUP @@ -134,8 +134,8 @@ body: | ; SOFT-DAG: %r{{[2-3]}} = COPY [[Y1]] ; HARD-DAG: %d0 = COPY [[X]] ; HARD-DAG: %d1 = COPY [[Y]] - ; SOFT: BLX $fmod, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1 - ; HARD: BLX $fmod, {{.*}}, implicit %d0, implicit %d1, implicit-def %d0 + ; SOFT: BL $fmod, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1 + ; HARD: BL $fmod, {{.*}}, implicit %d0, implicit %d1, implicit-def %d0 ; CHECK: ADJCALLSTACKUP ; CHECK-NOT: G_FREM %6(s64) = G_FREM %4, %5 @@ -170,8 +170,8 @@ body: | ; SOFT-DAG: %r1 = COPY [[Y]] ; HARD-DAG: %s0 = COPY [[X]] ; HARD-DAG: %s1 = COPY [[Y]] - ; SOFT: BLX $powf, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; HARD: BLX $powf, {{.*}}, implicit %s0, implicit %s1, implicit-def %s0 + ; SOFT: BL $powf, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; HARD: BL $powf, {{.*}}, implicit %s0, implicit %s1, implicit-def %s0 ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY %r0 ; HARD: [[R:%[0-9]+]]:_(s32) = COPY %s0 ; CHECK: ADJCALLSTACKUP @@ -229,8 +229,8 @@ body: | ; SOFT-DAG: %r{{[2-3]}} = COPY [[Y1]] ; HARD-DAG: %d0 = COPY [[X]] ; HARD-DAG: %d1 = COPY [[Y]] - ; SOFT: BLX $pow, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1 - ; HARD: BLX $pow, {{.*}}, implicit %d0, implicit %d1, implicit-def %d0 + ; SOFT: BL $pow, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1 + ; HARD: BL $pow, {{.*}}, implicit %d0, implicit %d1, implicit-def %d0 ; CHECK: ADJCALLSTACKUP ; CHECK-NOT: G_FPOW %6(s64) = G_FPOW %4, %5 @@ -264,8 +264,8 @@ body: | ; SOFT: ADJCALLSTACKDOWN ; SOFT-DAG: %r0 = COPY [[X]] ; SOFT-DAG: %r1 = COPY [[Y]] - ; SOFT-AEABI: BLX $__aeabi_fadd, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT-DEFAULT: BLX $__addsf3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-AEABI: BL $__aeabi_fadd, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: BL $__addsf3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY %r0 ; SOFT: ADJCALLSTACKUP ; SOFT-NOT: G_FADD @@ -315,8 +315,8 @@ body: | ; SOFT-DAG: %r{{[0-1]}} = COPY [[X1]] ; SOFT-DAG: %r{{[2-3]}} = COPY [[Y0]] ; SOFT-DAG: %r{{[2-3]}} = COPY [[Y1]] - ; SOFT-AEABI: BLX $__aeabi_dadd, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1 - ; SOFT-DEFAULT: BLX $__adddf3, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1 + ; SOFT-AEABI: BL $__aeabi_dadd, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1 + ; SOFT-DEFAULT: BL $__adddf3, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1 ; SOFT: ADJCALLSTACKUP ; SOFT-NOT: G_FADD %6(s64) = G_FADD %4, %5 @@ -419,8 +419,8 @@ body: | ; SOFT: ADJCALLSTACKDOWN ; SOFT-DAG: %r0 = COPY [[X]] ; SOFT-DAG: %r1 = COPY [[Y]] - ; SOFT-AEABI: BLX $__aeabi_fcmpeq, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT-DEFAULT: BLX $__eqsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-AEABI: BL $__aeabi_fcmpeq, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: BL $__eqsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 ; SOFT: ADJCALLSTACKUP ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32) @@ -460,8 +460,8 @@ body: | ; SOFT: ADJCALLSTACKDOWN ; SOFT-DAG: %r0 = COPY [[X]] ; SOFT-DAG: %r1 = COPY [[Y]] - ; SOFT-AEABI: BLX $__aeabi_fcmpgt, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT-DEFAULT: BLX $__gtsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-AEABI: BL $__aeabi_fcmpgt, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: BL $__gtsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 ; SOFT: ADJCALLSTACKUP ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32) @@ -501,8 +501,8 @@ body: | ; SOFT: ADJCALLSTACKDOWN ; SOFT-DAG: %r0 = COPY [[X]] ; SOFT-DAG: %r1 = COPY [[Y]] - ; SOFT-AEABI: BLX $__aeabi_fcmpge, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT-DEFAULT: BLX $__gesf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-AEABI: BL $__aeabi_fcmpge, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: BL $__gesf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 ; SOFT: ADJCALLSTACKUP ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32) @@ -542,8 +542,8 @@ body: | ; SOFT: ADJCALLSTACKDOWN ; SOFT-DAG: %r0 = COPY [[X]] ; SOFT-DAG: %r1 = COPY [[Y]] - ; SOFT-AEABI: BLX $__aeabi_fcmplt, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT-DEFAULT: BLX $__ltsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-AEABI: BL $__aeabi_fcmplt, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: BL $__ltsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 ; SOFT: ADJCALLSTACKUP ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32) @@ -583,8 +583,8 @@ body: | ; SOFT: ADJCALLSTACKDOWN ; SOFT-DAG: %r0 = COPY [[X]] ; SOFT-DAG: %r1 = COPY [[Y]] - ; SOFT-AEABI: BLX $__aeabi_fcmple, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT-DEFAULT: BLX $__lesf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-AEABI: BL $__aeabi_fcmple, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: BL $__lesf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 ; SOFT: ADJCALLSTACKUP ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32) @@ -624,8 +624,8 @@ body: | ; SOFT: ADJCALLSTACKDOWN ; SOFT-DAG: %r0 = COPY [[X]] ; SOFT-DAG: %r1 = COPY [[Y]] - ; SOFT-AEABI: BLX $__aeabi_fcmpun, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT-DEFAULT: BLX $__unordsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-AEABI: BL $__aeabi_fcmpun, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: BL $__unordsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 ; SOFT: ADJCALLSTACKUP ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 @@ -664,8 +664,8 @@ body: | ; SOFT: ADJCALLSTACKDOWN ; SOFT-DAG: %r0 = COPY [[X]] ; SOFT-DAG: %r1 = COPY [[Y]] - ; SOFT-AEABI: BLX $__aeabi_fcmple, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT-DEFAULT: BLX $__lesf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-AEABI: BL $__aeabi_fcmple, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: BL $__lesf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 ; SOFT: ADJCALLSTACKUP ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 @@ -705,8 +705,8 @@ body: | ; SOFT: ADJCALLSTACKDOWN ; SOFT-DAG: %r0 = COPY [[X]] ; SOFT-DAG: %r1 = COPY [[Y]] - ; SOFT-AEABI: BLX $__aeabi_fcmplt, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT-DEFAULT: BLX $__ltsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-AEABI: BL $__aeabi_fcmplt, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: BL $__ltsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 ; SOFT: ADJCALLSTACKUP ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 @@ -746,8 +746,8 @@ body: | ; SOFT: ADJCALLSTACKDOWN ; SOFT-DAG: %r0 = COPY [[X]] ; SOFT-DAG: %r1 = COPY [[Y]] - ; SOFT-AEABI: BLX $__aeabi_fcmpge, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT-DEFAULT: BLX $__gesf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-AEABI: BL $__aeabi_fcmpge, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: BL $__gesf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 ; SOFT: ADJCALLSTACKUP ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 @@ -787,8 +787,8 @@ body: | ; SOFT: ADJCALLSTACKDOWN ; SOFT-DAG: %r0 = COPY [[X]] ; SOFT-DAG: %r1 = COPY [[Y]] - ; SOFT-AEABI: BLX $__aeabi_fcmpgt, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT-DEFAULT: BLX $__gtsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-AEABI: BL $__aeabi_fcmpgt, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: BL $__gtsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 ; SOFT: ADJCALLSTACKUP ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 @@ -828,8 +828,8 @@ body: | ; SOFT: ADJCALLSTACKDOWN ; SOFT-DAG: %r0 = COPY [[X]] ; SOFT-DAG: %r1 = COPY [[Y]] - ; SOFT-AEABI: BLX $__aeabi_fcmpeq, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT-DEFAULT: BLX $__nesf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-AEABI: BL $__aeabi_fcmpeq, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: BL $__nesf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 ; SOFT: ADJCALLSTACKUP ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 @@ -869,8 +869,8 @@ body: | ; SOFT: ADJCALLSTACKDOWN ; SOFT-DAG: %r0 = COPY [[X]] ; SOFT-DAG: %r1 = COPY [[Y]] - ; SOFT-AEABI: BLX $__aeabi_fcmpun, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT-DEFAULT: BLX $__unordsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-AEABI: BL $__aeabi_fcmpun, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: BL $__unordsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 ; SOFT: ADJCALLSTACKUP ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32) @@ -910,8 +910,8 @@ body: | ; SOFT: ADJCALLSTACKDOWN ; SOFT-DAG: %r0 = COPY [[X]] ; SOFT-DAG: %r1 = COPY [[Y]] - ; SOFT-AEABI: BLX $__aeabi_fcmpgt, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT-DEFAULT: BLX $__gtsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-AEABI: BL $__aeabi_fcmpgt, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: BL $__gtsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 ; SOFT: [[RET1:%[0-9]+]]:_(s32) = COPY %r0 ; SOFT: ADJCALLSTACKUP ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 @@ -920,8 +920,8 @@ body: | ; SOFT: ADJCALLSTACKDOWN ; SOFT-DAG: %r0 = COPY [[X]] ; SOFT-DAG: %r1 = COPY [[Y]] - ; SOFT-AEABI: BLX $__aeabi_fcmplt, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT-DEFAULT: BLX $__ltsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-AEABI: BL $__aeabi_fcmplt, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: BL $__ltsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 ; SOFT: [[RET2:%[0-9]+]]:_(s32) = COPY %r0 ; SOFT: ADJCALLSTACKUP ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 @@ -966,8 +966,8 @@ body: | ; SOFT: ADJCALLSTACKDOWN ; SOFT-DAG: %r0 = COPY [[X]] ; SOFT-DAG: %r1 = COPY [[Y]] - ; SOFT-AEABI: BLX $__aeabi_fcmpeq, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT-DEFAULT: BLX $__eqsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-AEABI: BL $__aeabi_fcmpeq, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: BL $__eqsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 ; SOFT: [[RET1:%[0-9]+]]:_(s32) = COPY %r0 ; SOFT: ADJCALLSTACKUP ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 @@ -976,8 +976,8 @@ body: | ; SOFT: ADJCALLSTACKDOWN ; SOFT-DAG: %r0 = COPY [[X]] ; SOFT-DAG: %r1 = COPY [[Y]] - ; SOFT-AEABI: BLX $__aeabi_fcmpun, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 - ; SOFT-DEFAULT: BLX $__unordsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-AEABI: BL $__aeabi_fcmpun, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: BL $__unordsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 ; SOFT: [[RET2:%[0-9]+]]:_(s32) = COPY %r0 ; SOFT: ADJCALLSTACKUP ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 @@ -1126,8 +1126,8 @@ body: | ; SOFT-DAG: %r1 = COPY [[X1]] ; SOFT-DAG: %r2 = COPY [[Y0]] ; SOFT-DAG: %r3 = COPY [[Y1]] - ; SOFT-AEABI: BLX $__aeabi_dcmpeq, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 - ; SOFT-DEFAULT: BLX $__eqdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT-AEABI: BL $__aeabi_dcmpeq, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT-DEFAULT: BL $__eqdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 ; SOFT: ADJCALLSTACKUP ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32) @@ -1181,8 +1181,8 @@ body: | ; SOFT-DAG: %r1 = COPY [[X1]] ; SOFT-DAG: %r2 = COPY [[Y0]] ; SOFT-DAG: %r3 = COPY [[Y1]] - ; SOFT-AEABI: BLX $__aeabi_dcmpgt, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 - ; SOFT-DEFAULT: BLX $__gtdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT-AEABI: BL $__aeabi_dcmpgt, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT-DEFAULT: BL $__gtdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 ; SOFT: ADJCALLSTACKUP ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32) @@ -1236,8 +1236,8 @@ body: | ; SOFT-DAG: %r1 = COPY [[X1]] ; SOFT-DAG: %r2 = COPY [[Y0]] ; SOFT-DAG: %r3 = COPY [[Y1]] - ; SOFT-AEABI: BLX $__aeabi_dcmpge, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 - ; SOFT-DEFAULT: BLX $__gedf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT-AEABI: BL $__aeabi_dcmpge, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT-DEFAULT: BL $__gedf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 ; SOFT: ADJCALLSTACKUP ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32) @@ -1291,8 +1291,8 @@ body: | ; SOFT-DAG: %r1 = COPY [[X1]] ; SOFT-DAG: %r2 = COPY [[Y0]] ; SOFT-DAG: %r3 = COPY [[Y1]] - ; SOFT-AEABI: BLX $__aeabi_dcmplt, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 - ; SOFT-DEFAULT: BLX $__ltdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT-AEABI: BL $__aeabi_dcmplt, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT-DEFAULT: BL $__ltdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 ; SOFT: ADJCALLSTACKUP ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32) @@ -1346,8 +1346,8 @@ body: | ; SOFT-DAG: %r1 = COPY [[X1]] ; SOFT-DAG: %r2 = COPY [[Y0]] ; SOFT-DAG: %r3 = COPY [[Y1]] - ; SOFT-AEABI: BLX $__aeabi_dcmple, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 - ; SOFT-DEFAULT: BLX $__ledf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT-AEABI: BL $__aeabi_dcmple, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT-DEFAULT: BL $__ledf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 ; SOFT: ADJCALLSTACKUP ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32) @@ -1401,8 +1401,8 @@ body: | ; SOFT-DAG: %r1 = COPY [[X1]] ; SOFT-DAG: %r2 = COPY [[Y0]] ; SOFT-DAG: %r3 = COPY [[Y1]] - ; SOFT-AEABI: BLX $__aeabi_dcmpun, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 - ; SOFT-DEFAULT: BLX $__unorddf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT-AEABI: BL $__aeabi_dcmpun, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT-DEFAULT: BL $__unorddf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 ; SOFT: ADJCALLSTACKUP ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 @@ -1455,8 +1455,8 @@ body: | ; SOFT-DAG: %r1 = COPY [[X1]] ; SOFT-DAG: %r2 = COPY [[Y0]] ; SOFT-DAG: %r3 = COPY [[Y1]] - ; SOFT-AEABI: BLX $__aeabi_dcmple, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 - ; SOFT-DEFAULT: BLX $__ledf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT-AEABI: BL $__aeabi_dcmple, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT-DEFAULT: BL $__ledf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 ; SOFT: ADJCALLSTACKUP ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 @@ -1510,8 +1510,8 @@ body: | ; SOFT-DAG: %r1 = COPY [[X1]] ; SOFT-DAG: %r2 = COPY [[Y0]] ; SOFT-DAG: %r3 = COPY [[Y1]] - ; SOFT-AEABI: BLX $__aeabi_dcmplt, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 - ; SOFT-DEFAULT: BLX $__ltdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT-AEABI: BL $__aeabi_dcmplt, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT-DEFAULT: BL $__ltdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 ; SOFT: ADJCALLSTACKUP ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 @@ -1565,8 +1565,8 @@ body: | ; SOFT-DAG: %r1 = COPY [[X1]] ; SOFT-DAG: %r2 = COPY [[Y0]] ; SOFT-DAG: %r3 = COPY [[Y1]] - ; SOFT-AEABI: BLX $__aeabi_dcmpge, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 - ; SOFT-DEFAULT: BLX $__gedf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT-AEABI: BL $__aeabi_dcmpge, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT-DEFAULT: BL $__gedf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 ; SOFT: ADJCALLSTACKUP ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 @@ -1620,8 +1620,8 @@ body: | ; SOFT-DAG: %r1 = COPY [[X1]] ; SOFT-DAG: %r2 = COPY [[Y0]] ; SOFT-DAG: %r3 = COPY [[Y1]] - ; SOFT-AEABI: BLX $__aeabi_dcmpgt, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 - ; SOFT-DEFAULT: BLX $__gtdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT-AEABI: BL $__aeabi_dcmpgt, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT-DEFAULT: BL $__gtdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 ; SOFT: ADJCALLSTACKUP ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 @@ -1675,8 +1675,8 @@ body: | ; SOFT-DAG: %r1 = COPY [[X1]] ; SOFT-DAG: %r2 = COPY [[Y0]] ; SOFT-DAG: %r3 = COPY [[Y1]] - ; SOFT-AEABI: BLX $__aeabi_dcmpeq, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 - ; SOFT-DEFAULT: BLX $__nedf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT-AEABI: BL $__aeabi_dcmpeq, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT-DEFAULT: BL $__nedf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 ; SOFT: ADJCALLSTACKUP ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 @@ -1730,8 +1730,8 @@ body: | ; SOFT-DAG: %r1 = COPY [[X1]] ; SOFT-DAG: %r2 = COPY [[Y0]] ; SOFT-DAG: %r3 = COPY [[Y1]] - ; SOFT-AEABI: BLX $__aeabi_dcmpun, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 - ; SOFT-DEFAULT: BLX $__unorddf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT-AEABI: BL $__aeabi_dcmpun, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT-DEFAULT: BL $__unorddf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0 ; SOFT: ADJCALLSTACKUP ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32) @@ -1785,8 +1785,8 @@ body: | ; SOFT-DAG: %r1 = COPY [[X1]] ; SOFT-DAG: %r2 = COPY [[Y0]] ; SOFT-DAG: %r3 = COPY [[Y1]] - ; SOFT-AEABI: BLX $__aeabi_dcmpgt, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 - ; SOFT-DEFAULT: BLX $__gtdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT-AEABI: BL $__aeabi_dcmpgt, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT-DEFAULT: BL $__gtdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 ; SOFT: [[RET1:%[0-9]+]]:_(s32) = COPY %r0 ; SOFT: ADJCALLSTACKUP ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 @@ -1797,8 +1797,8 @@ body: | ; SOFT-DAG: %r1 = COPY [[X1]] ; SOFT-DAG: %r2 = COPY [[Y0]] ; SOFT-DAG: %r3 = COPY [[Y1]] - ; SOFT-AEABI: BLX $__aeabi_dcmplt, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 - ; SOFT-DEFAULT: BLX $__ltdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT-AEABI: BL $__aeabi_dcmplt, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT-DEFAULT: BL $__ltdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 ; SOFT: [[RET2:%[0-9]+]]:_(s32) = COPY %r0 ; SOFT: ADJCALLSTACKUP ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 @@ -1857,8 +1857,8 @@ body: | ; SOFT-DAG: %r1 = COPY [[X1]] ; SOFT-DAG: %r2 = COPY [[Y0]] ; SOFT-DAG: %r3 = COPY [[Y1]] - ; SOFT-AEABI: BLX $__aeabi_dcmpeq, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 - ; SOFT-DEFAULT: BLX $__eqdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT-AEABI: BL $__aeabi_dcmpeq, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT-DEFAULT: BL $__eqdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 ; SOFT: [[RET1:%[0-9]+]]:_(s32) = COPY %r0 ; SOFT: ADJCALLSTACKUP ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 @@ -1869,8 +1869,8 @@ body: | ; SOFT-DAG: %r1 = COPY [[X1]] ; SOFT-DAG: %r2 = COPY [[Y0]] ; SOFT-DAG: %r3 = COPY [[Y1]] - ; SOFT-AEABI: BLX $__aeabi_dcmpun, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 - ; SOFT-DEFAULT: BLX $__unorddf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT-AEABI: BL $__aeabi_dcmpun, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 + ; SOFT-DEFAULT: BL $__unorddf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 ; SOFT: [[RET2:%[0-9]+]]:_(s32) = COPY %r0 ; SOFT: ADJCALLSTACKUP ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll b/llvm/test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll index d0fabe93c81d..92c4e2905d88 100644 --- a/llvm/test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll +++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll @@ -10,7 +10,7 @@ define arm_aapcscc i32* @test_call_simple_reg_params(i32 *%a, i32 %b) { ; CHECK: ADJCALLSTACKDOWN 0, 0, 14, _, implicit-def %sp, implicit %sp ; CHECK-DAG: %r0 = COPY [[BVREG]] ; CHECK-DAG: %r1 = COPY [[AVREG]] -; CHECK: BLX @simple_reg_params_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit-def %r0 +; CHECK: BL @simple_reg_params_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit-def %r0 ; CHECK: [[RVREG:%[0-9]+]]:_(p0) = COPY %r0 ; CHECK: ADJCALLSTACKUP 0, 0, 14, _, implicit-def %sp, implicit %sp ; CHECK: %r0 = COPY [[RVREG]] @@ -39,7 +39,7 @@ define arm_aapcscc i32* @test_call_simple_stack_params(i32 *%a, i32 %b) { ; CHECK: [[OFF2:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 ; CHECK: [[FI2:%[0-9]+]]:_(p0) = G_GEP [[SP2]], [[OFF2]](s32) ; CHECK: G_STORE [[AVREG]](p0), [[FI2]](p0){{.*}}store 4 -; CHECK: BLX @simple_stack_params_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 +; CHECK: BL @simple_stack_params_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 ; CHECK: [[RVREG:%[0-9]+]]:_(p0) = COPY %r0 ; CHECK: ADJCALLSTACKUP 8, 0, 14, _, implicit-def %sp, implicit %sp ; CHECK: %r0 = COPY [[RVREG]] @@ -93,7 +93,7 @@ define arm_aapcscc signext i16 @test_call_ext_params(i8 %a, i16 %b, i1 %c) { ; CHECK: [[FI5:%[0-9]+]]:_(p0) = G_GEP [[SP5]], [[OFF5]](s32) ; CHECK: [[ZEXTC:%[0-9]+]]:_(s32) = G_ZEXT [[CVREG]] ; CHECK: G_STORE [[ZEXTC]](s32), [[FI5]](p0){{.*}}store 4 -; CHECK: BLX @ext_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 +; CHECK: BL @ext_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 ; CHECK: [[R0VREG:%[0-9]+]]:_(s32) = COPY %r0 ; CHECK: [[RVREG:%[0-9]+]]:_(s16) = G_TRUNC [[R0VREG]] ; CHECK: ADJCALLSTACKUP 20, 0, 14, _, implicit-def %sp, implicit %sp @@ -114,7 +114,7 @@ define arm_aapcs_vfpcc double @test_call_vfpcc_fp_params(double %a, float %b) { ; CHECK: ADJCALLSTACKDOWN 0, 0, 14, _, implicit-def %sp, implicit %sp ; CHECK-DAG: %s0 = COPY [[BVREG]] ; CHECK-DAG: %d1 = COPY [[AVREG]] -; CHECK: BLX @vfpcc_fp_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %s0, implicit %d1, implicit-def %d0 +; CHECK: BL @vfpcc_fp_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %s0, implicit %d1, implicit-def %d0 ; CHECK: [[RVREG:%[0-9]+]]:_(s64) = COPY %d0 ; CHECK: ADJCALLSTACKUP 0, 0, 14, _, implicit-def %sp, implicit %sp ; CHECK: %d0 = COPY [[RVREG]] @@ -148,7 +148,7 @@ define arm_aapcscc double @test_call_aapcs_fp_params(double %a, float %b) { ; CHECK: [[OFF2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; CHECK: [[FI2:%[0-9]+]]:_(p0) = G_GEP [[SP2]], [[OFF2]](s32) ; CHECK: G_STORE [[AVREG]](s64), [[FI2]](p0){{.*}}store 8 -; CHECK: BLX @aapcscc_fp_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1 +; CHECK: BL @aapcscc_fp_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1 ; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY %r0 ; CHECK-DAG: [[R2:%[0-9]+]]:_(s32) = COPY %r1 ; LITTLE: [[RVREG:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R1]](s32), [[R2]](s32) @@ -172,7 +172,7 @@ define arm_aapcs_vfpcc float @test_call_different_call_conv(float %x) { ; CHECK: [[X:%[0-9]+]]:_(s32) = COPY %s0 ; CHECK: ADJCALLSTACKDOWN 0, 0, 14, _, implicit-def %sp, implicit %sp ; CHECK: %r0 = COPY [[X]] -; CHECK: BLX @different_call_conv_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit-def %r0 +; CHECK: BL @different_call_conv_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit-def %r0 ; CHECK: [[R:%[0-9]+]]:_(s32) = COPY %r0 ; CHECK: ADJCALLSTACKUP 0, 0, 14, _, implicit-def %sp, implicit %sp ; CHECK: %s0 = COPY [[R]] @@ -194,7 +194,7 @@ define arm_aapcscc [3 x i32] @test_tiny_int_arrays([2 x i32] %arr) { ; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARG_ARR]](s64) ; CHECK: %r0 = COPY [[R0]] ; CHECK: %r1 = COPY [[R1]] -; CHECK: BLX @tiny_int_arrays_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit-def %r0, implicit-def %r1 +; CHECK: BL @tiny_int_arrays_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit-def %r0, implicit-def %r1 ; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY %r0 ; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY %r1 ; CHECK: [[R2:%[0-9]+]]:_(s32) = COPY %r2 @@ -231,7 +231,7 @@ define arm_aapcscc void @test_multiple_int_arrays([2 x i32] %arr0, [2 x i32] %ar ; CHECK: %r1 = COPY [[R1]] ; CHECK: %r2 = COPY [[R2]] ; CHECK: %r3 = COPY [[R3]] -; CHECK: BLX @multiple_int_arrays_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3 +; CHECK: BL @multiple_int_arrays_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3 ; CHECK: ADJCALLSTACKUP 0, 0, 14, _, implicit-def %sp, implicit %sp ; CHECK: BX_RET 14, _ entry: @@ -274,7 +274,7 @@ define arm_aapcscc void @test_large_int_arrays([20 x i32] %arr) { ; CHECK: [[OFF_LAST_ELEMENT:%[0-9]+]]:_(s32) = G_CONSTANT i32 60 ; CHECK: [[LAST_STACK_ARG_ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFF_LAST_ELEMENT]](s32) ; CHECK: G_STORE [[LAST_STACK_ELEMENT]](s32), [[LAST_STACK_ARG_ADDR]]{{.*}}store 4 -; CHECK: BLX @large_int_arrays_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3 +; CHECK: BL @large_int_arrays_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3 ; CHECK: ADJCALLSTACKUP 64, 0, 14, _, implicit-def %sp, implicit %sp ; CHECK: BX_RET 14, _ entry: @@ -316,7 +316,7 @@ define arm_aapcscc [2 x float] @test_fp_arrays_aapcs([3 x double] %arr) { ; CHECK: [[ARR2_OFFSET:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[ARR2_ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[ARR2_OFFSET]](s32) ; CHECK: G_STORE [[ARR2]](s64), [[ARR2_ADDR]](p0){{.*}}store 8 -; CHECK: BLX @fp_arrays_aapcs_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1 +; CHECK: BL @fp_arrays_aapcs_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1 ; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY %r0 ; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY %r1 ; CHECK: [[R_MERGED:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32) @@ -383,7 +383,7 @@ define arm_aapcs_vfpcc [4 x float] @test_fp_arrays_aapcs_vfp([3 x double] %x, [3 ; CHECK: [[Z3_OFFSET:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 ; CHECK: [[Z3_ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[Z3_OFFSET]](s32) ; CHECK: G_STORE [[Z3]](s64), [[Z3_ADDR]](p0){{.*}}store 8 -; CHECK: BLX @fp_arrays_aapcs_vfp_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %d0, implicit %d1, implicit %d2, implicit %s6, implicit %s7, implicit %s8, implicit-def %s0, implicit-def %s1, implicit-def %s2, implicit-def %s3 +; CHECK: BL @fp_arrays_aapcs_vfp_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %d0, implicit %d1, implicit %d2, implicit %s6, implicit %s7, implicit %s8, implicit-def %s0, implicit-def %s1, implicit-def %s2, implicit-def %s3 ; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY %s0 ; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY %s1 ; CHECK: [[R2:%[0-9]+]]:_(s32) = COPY %s2 @@ -436,7 +436,7 @@ define arm_aapcscc [2 x i32*] @test_tough_arrays([6 x [4 x i32]] %arr) { ; CHECK: [[OFF_LAST_ELEMENT:%[0-9]+]]:_(s32) = G_CONSTANT i32 76 ; CHECK: [[LAST_STACK_ARG_ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFF_LAST_ELEMENT]](s32) ; CHECK: G_STORE [[LAST_STACK_ELEMENT]](s32), [[LAST_STACK_ARG_ADDR]]{{.*}}store 4 -; CHECK: BLX @tough_arrays_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1 +; CHECK: BL @tough_arrays_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1 ; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY %r0 ; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY %r1 ; CHECK: [[RES_ARR:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32) @@ -462,7 +462,7 @@ define arm_aapcscc {i32, i32} @test_structs({i32, i32} %x) { ; CHECK: [[X0:%[0-9]+]]:_(s32), [[X1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[X]](s64) ; CHECK-DAG: %r0 = COPY [[X0]](s32) ; CHECK-DAG: %r1 = COPY [[X1]](s32) -; CHECK: BLX @structs_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit-def %r0, implicit-def %r1 +; CHECK: BL @structs_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit-def %r0, implicit-def %r1 ; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY %r0 ; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY %r1 ; CHECK: [[R:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32)