forked from OSchip/llvm-project
[ARM] More MVE compare vector splat combines for ANDs
Adds some extra r register compare combines, this time for ANDs. Differential Revision: https://reviews.llvm.org/D65062 llvm-svn: 366928
This commit is contained in:
David Green
parent
f548398674
commit
b342bddbe2
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@ -3019,6 +3019,13 @@ multiclass unpred_vcmp_r<SDPatternOperator opnode, string suffix, int fc> {
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(v8i1 (!cast<Instruction>("MVE_VCMP"#suffix#"16") (v8i16 MQPR:$v1), (v8i16 MQPR:$v2), fc, 1, VCCR:$p1))>;
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def : Pat<(v4i1 (and (v4i1 VCCR:$p1), (v4i1 (opnode (v4i32 MQPR:$v1), (v4i32 MQPR:$v2))))),
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(v4i1 (!cast<Instruction>("MVE_VCMP"#suffix#"32") (v4i32 MQPR:$v1), (v4i32 MQPR:$v2), fc, 1, VCCR:$p1))>;
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def : Pat<(v16i1 (and (v16i1 VCCR:$p1), (v16i1 (opnode (v16i8 MQPR:$v1), (v16i8 (ARMvdup GPR:$v2)))))),
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(v16i1 (!cast<Instruction>("MVE_VCMP"#suffix#"8r") (v16i8 MQPR:$v1), (i32 GPR:$v2), fc, 1, VCCR:$p1))>;
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def : Pat<(v8i1 (and (v8i1 VCCR:$p1), (v8i1 (opnode (v8i16 MQPR:$v1), (v8i16 (ARMvdup GPR:$v2)))))),
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(v8i1 (!cast<Instruction>("MVE_VCMP"#suffix#"16r") (v8i16 MQPR:$v1), (i32 GPR:$v2), fc, 1, VCCR:$p1))>;
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def : Pat<(v4i1 (and (v4i1 VCCR:$p1), (v4i1 (opnode (v4i32 MQPR:$v1), (v4i32 (ARMvdup GPR:$v2)))))),
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(v4i1 (!cast<Instruction>("MVE_VCMP"#suffix#"32r") (v4i32 MQPR:$v1), (i32 GPR:$v2), fc, 1, VCCR:$p1))>;
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}
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multiclass unpred_vcmpf_z<SDPatternOperator opnode, int fc> {
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@ -3048,6 +3055,11 @@ multiclass unpred_vcmpf_r<SDPatternOperator opnode, int fc> {
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(v8i1 (MVE_VCMPf16 (v8f16 MQPR:$v1), (v8f16 MQPR:$v2), fc, 1, VCCR:$p1))>;
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def : Pat<(v4i1 (and (v4i1 VCCR:$p1), (v4i1 (opnode (v4f32 MQPR:$v1), (v4f32 MQPR:$v2))))),
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(v4i1 (MVE_VCMPf32 (v4f32 MQPR:$v1), (v4f32 MQPR:$v2), fc, 1, VCCR:$p1))>;
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def : Pat<(v8i1 (and (v8i1 VCCR:$p1), (v8i1 (opnode (v8f16 MQPR:$v1), (v8f16 (ARMvdup HPR:$v2)))))),
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(v8i1 (MVE_VCMPf16r (v8f16 MQPR:$v1), (i32 (COPY_TO_REGCLASS (f16 HPR:$v2), rGPR)), fc, 1, VCCR:$p1))>;
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def : Pat<(v4i1 (and (v4i1 VCCR:$p1), (v4i1 (opnode (v4f32 MQPR:$v1), (v4f32 (ARMvdup SPR:$v2)))))),
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(v4i1 (MVE_VCMPf32r (v4f32 MQPR:$v1), (i32 (COPY_TO_REGCLASS (f32 SPR:$v2), rGPR)), fc, 1, VCCR:$p1))>;
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}
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let Predicates = [HasMVEInt] in {
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@ -319,6 +319,190 @@ entry:
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}
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define arm_aapcs_vfpcc <4 x i32> @cmpeqr_v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c) {
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; CHECK-LABEL: cmpeqr_v4i1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vcmp.i32 eq, q0, zr
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vcmpt.i32 eq, q1, r0
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; CHECK-NEXT: vpsel q0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%c1 = icmp eq <4 x i32> %a, zeroinitializer
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%i = insertelement <4 x i32> undef, i32 %c, i32 0
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%sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer
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%c2 = icmp eq <4 x i32> %b, %sp
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%o = and <4 x i1> %c1, %c2
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%s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
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ret <4 x i32> %s
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}
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define arm_aapcs_vfpcc <4 x i32> @cmpner_v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c) {
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; CHECK-LABEL: cmpner_v4i1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vcmp.i32 eq, q0, zr
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vcmpt.i32 ne, q1, r0
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; CHECK-NEXT: vpsel q0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%c1 = icmp eq <4 x i32> %a, zeroinitializer
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%i = insertelement <4 x i32> undef, i32 %c, i32 0
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%sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer
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%c2 = icmp ne <4 x i32> %b, %sp
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%o = and <4 x i1> %c1, %c2
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%s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
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ret <4 x i32> %s
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}
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define arm_aapcs_vfpcc <4 x i32> @cmpsltr_v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c) {
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; CHECK-LABEL: cmpsltr_v4i1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vcmp.i32 eq, q0, zr
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; CHECK-NEXT: vdup.32 q2, r0
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vcmpt.s32 gt, q2, q1
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; CHECK-NEXT: vpsel q0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%c1 = icmp eq <4 x i32> %a, zeroinitializer
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%i = insertelement <4 x i32> undef, i32 %c, i32 0
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%sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer
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%c2 = icmp slt <4 x i32> %b, %sp
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%o = and <4 x i1> %c1, %c2
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%s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
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ret <4 x i32> %s
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}
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define arm_aapcs_vfpcc <4 x i32> @cmpsgtr_v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c) {
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; CHECK-LABEL: cmpsgtr_v4i1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vcmp.i32 eq, q0, zr
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vcmpt.s32 gt, q1, r0
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; CHECK-NEXT: vpsel q0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%c1 = icmp eq <4 x i32> %a, zeroinitializer
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%i = insertelement <4 x i32> undef, i32 %c, i32 0
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%sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer
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%c2 = icmp sgt <4 x i32> %b, %sp
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%o = and <4 x i1> %c1, %c2
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%s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
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ret <4 x i32> %s
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}
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define arm_aapcs_vfpcc <4 x i32> @cmpsler_v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c) {
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; CHECK-LABEL: cmpsler_v4i1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vcmp.i32 eq, q0, zr
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; CHECK-NEXT: vdup.32 q2, r0
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vcmpt.s32 ge, q2, q1
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; CHECK-NEXT: vpsel q0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%c1 = icmp eq <4 x i32> %a, zeroinitializer
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%i = insertelement <4 x i32> undef, i32 %c, i32 0
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%sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer
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%c2 = icmp sle <4 x i32> %b, %sp
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%o = and <4 x i1> %c1, %c2
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%s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
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ret <4 x i32> %s
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}
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define arm_aapcs_vfpcc <4 x i32> @cmpsger_v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c) {
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; CHECK-LABEL: cmpsger_v4i1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vcmp.i32 eq, q0, zr
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vcmpt.s32 ge, q1, r0
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; CHECK-NEXT: vpsel q0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%c1 = icmp eq <4 x i32> %a, zeroinitializer
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%i = insertelement <4 x i32> undef, i32 %c, i32 0
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%sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer
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%c2 = icmp sge <4 x i32> %b, %sp
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%o = and <4 x i1> %c1, %c2
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%s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
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ret <4 x i32> %s
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}
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define arm_aapcs_vfpcc <4 x i32> @cmpultr_v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c) {
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; CHECK-LABEL: cmpultr_v4i1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vcmp.i32 eq, q0, zr
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; CHECK-NEXT: vdup.32 q2, r0
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vcmpt.u32 hi, q2, q1
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; CHECK-NEXT: vpsel q0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%c1 = icmp eq <4 x i32> %a, zeroinitializer
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%i = insertelement <4 x i32> undef, i32 %c, i32 0
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%sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer
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%c2 = icmp ult <4 x i32> %b, %sp
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%o = and <4 x i1> %c1, %c2
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%s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
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ret <4 x i32> %s
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}
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define arm_aapcs_vfpcc <4 x i32> @cmpugtr_v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c) {
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; CHECK-LABEL: cmpugtr_v4i1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vcmp.i32 eq, q0, zr
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vcmpt.u32 hi, q1, r0
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; CHECK-NEXT: vpsel q0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%c1 = icmp eq <4 x i32> %a, zeroinitializer
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%i = insertelement <4 x i32> undef, i32 %c, i32 0
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%sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer
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%c2 = icmp ugt <4 x i32> %b, %sp
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%o = and <4 x i1> %c1, %c2
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%s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
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ret <4 x i32> %s
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}
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define arm_aapcs_vfpcc <4 x i32> @cmpuler_v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c) {
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; CHECK-LABEL: cmpuler_v4i1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vcmp.i32 eq, q0, zr
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; CHECK-NEXT: vdup.32 q2, r0
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vcmpt.u32 cs, q2, q1
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; CHECK-NEXT: vpsel q0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%c1 = icmp eq <4 x i32> %a, zeroinitializer
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%i = insertelement <4 x i32> undef, i32 %c, i32 0
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%sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer
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%c2 = icmp ule <4 x i32> %b, %sp
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%o = and <4 x i1> %c1, %c2
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%s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
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ret <4 x i32> %s
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}
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define arm_aapcs_vfpcc <4 x i32> @cmpuger_v4i1(<4 x i32> %a, <4 x i32> %b, i32 %c) {
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; CHECK-LABEL: cmpuger_v4i1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vcmp.i32 eq, q0, zr
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vcmpt.u32 cs, q1, r0
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; CHECK-NEXT: vpsel q0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%c1 = icmp eq <4 x i32> %a, zeroinitializer
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%i = insertelement <4 x i32> undef, i32 %c, i32 0
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%sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer
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%c2 = icmp uge <4 x i32> %b, %sp
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%o = and <4 x i1> %c1, %c2
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%s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
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ret <4 x i32> %s
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}
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define arm_aapcs_vfpcc <8 x i16> @cmpeqz_v8i1(<8 x i16> %a, <8 x i16> %b) {
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@ -352,6 +536,24 @@ entry:
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ret <8 x i16> %s
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}
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define arm_aapcs_vfpcc <8 x i16> @cmpeqr_v8i1(<8 x i16> %a, <8 x i16> %b, i16 %c) {
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; CHECK-LABEL: cmpeqr_v8i1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vcmp.i16 eq, q0, zr
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vcmpt.i16 eq, q1, r0
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; CHECK-NEXT: vpsel q0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%c1 = icmp eq <8 x i16> %a, zeroinitializer
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%i = insertelement <8 x i16> undef, i16 %c, i32 0
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%sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer
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%c2 = icmp eq <8 x i16> %b, %sp
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%o = and <8 x i1> %c1, %c2
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%s = select <8 x i1> %o, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %s
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}
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define arm_aapcs_vfpcc <16 x i8> @cmpeqz_v16i1(<16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: cmpeqz_v16i1:
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@ -384,6 +586,24 @@ entry:
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ret <16 x i8> %s
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}
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define arm_aapcs_vfpcc <16 x i8> @cmpeqr_v16i1(<16 x i8> %a, <16 x i8> %b, i8 %c) {
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; CHECK-LABEL: cmpeqr_v16i1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vcmp.i8 eq, q0, zr
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vcmpt.i8 eq, q1, r0
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; CHECK-NEXT: vpsel q0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%c1 = icmp eq <16 x i8> %a, zeroinitializer
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%i = insertelement <16 x i8> undef, i8 %c, i32 0
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%sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer
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%c2 = icmp eq <16 x i8> %b, %sp
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%o = and <16 x i1> %c1, %c2
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%s = select <16 x i1> %o, <16 x i8> %a, <16 x i8> %b
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ret <16 x i8> %s
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}
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define arm_aapcs_vfpcc <2 x i64> @cmpeqz_v2i1(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: cmpeqz_v2i1:
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@ -479,4 +699,60 @@ entry:
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ret <2 x i64> %s
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}
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define arm_aapcs_vfpcc <2 x i64> @cmpeqr_v2i1(<2 x i64> %a, <2 x i64> %b, i64 %c) {
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; CHECK-LABEL: cmpeqr_v2i1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov r2, s5
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; CHECK-NEXT: vmov r3, s4
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; CHECK-NEXT: eors r2, r1
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; CHECK-NEXT: eors r3, r0
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; CHECK-NEXT: orrs r2, r3
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; CHECK-NEXT: clz r2, r2
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; CHECK-NEXT: lsrs r2, r2, #5
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; CHECK-NEXT: it ne
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; CHECK-NEXT: movne.w r2, #-1
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; CHECK-NEXT: vmov.32 q2[0], r2
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; CHECK-NEXT: vmov.32 q2[1], r2
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; CHECK-NEXT: vmov r2, s7
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; CHECK-NEXT: eors r1, r2
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; CHECK-NEXT: vmov r2, s6
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; CHECK-NEXT: eors r0, r2
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; CHECK-NEXT: orrs r0, r1
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; CHECK-NEXT: vmov r1, s0
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; CHECK-NEXT: clz r0, r0
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; CHECK-NEXT: lsrs r0, r0, #5
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; CHECK-NEXT: it ne
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; CHECK-NEXT: movne.w r0, #-1
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; CHECK-NEXT: vmov.32 q2[2], r0
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; CHECK-NEXT: vmov.32 q2[3], r0
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; CHECK-NEXT: vmov r0, s1
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; CHECK-NEXT: orrs r0, r1
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; CHECK-NEXT: vmov r1, s2
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; CHECK-NEXT: clz r0, r0
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; CHECK-NEXT: lsrs r0, r0, #5
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; CHECK-NEXT: it ne
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; CHECK-NEXT: movne.w r0, #-1
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; CHECK-NEXT: vmov.32 q3[0], r0
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; CHECK-NEXT: vmov.32 q3[1], r0
|
||||
; CHECK-NEXT: vmov r0, s3
|
||||
; CHECK-NEXT: orrs r0, r1
|
||||
; CHECK-NEXT: clz r0, r0
|
||||
; CHECK-NEXT: lsrs r0, r0, #5
|
||||
; CHECK-NEXT: it ne
|
||||
; CHECK-NEXT: movne.w r0, #-1
|
||||
; CHECK-NEXT: vmov.32 q3[2], r0
|
||||
; CHECK-NEXT: vmov.32 q3[3], r0
|
||||
; CHECK-NEXT: vand q2, q3, q2
|
||||
; CHECK-NEXT: vbic q1, q1, q2
|
||||
; CHECK-NEXT: vand q0, q0, q2
|
||||
; CHECK-NEXT: vorr q0, q0, q1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%c1 = icmp eq <2 x i64> %a, zeroinitializer
|
||||
%i = insertelement <2 x i64> undef, i64 %c, i32 0
|
||||
%sp = shufflevector <2 x i64> %i, <2 x i64> undef, <2 x i32> zeroinitializer
|
||||
%c2 = icmp eq <2 x i64> %b, %sp
|
||||
%o = and <2 x i1> %c1, %c2
|
||||
%s = select <2 x i1> %o, <2 x i64> %a, <2 x i64> %b
|
||||
ret <2 x i64> %s
|
||||
}
|
||||
|
|
|
|||
|
|
@ -123,7 +123,7 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_one_v4f32(<4 x float> %src, float %src2
|
|||
; CHECK-MVEFP-NEXT: vdup.32 q1, r0
|
||||
; CHECK-MVEFP-NEXT: vcmp.f32 le, q1, q0
|
||||
; CHECK-MVEFP-NEXT: vpst
|
||||
; CHECK-MVEFP-NEXT: vcmpt.f32 le, q0, q1
|
||||
; CHECK-MVEFP-NEXT: vcmpt.f32 le, q0, r0
|
||||
; CHECK-MVEFP-NEXT: vmrs r0, p0
|
||||
; CHECK-MVEFP-NEXT: eors r0, r1
|
||||
; CHECK-MVEFP-NEXT: vmsr p0, r0
|
||||
|
|
@ -436,7 +436,7 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_ueq_v4f32(<4 x float> %src, float %src2
|
|||
; CHECK-MVEFP-NEXT: vdup.32 q1, r0
|
||||
; CHECK-MVEFP-NEXT: vcmp.f32 le, q1, q0
|
||||
; CHECK-MVEFP-NEXT: vpst
|
||||
; CHECK-MVEFP-NEXT: vcmpt.f32 le, q0, q1
|
||||
; CHECK-MVEFP-NEXT: vcmpt.f32 le, q0, r0
|
||||
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
|
||||
; CHECK-MVEFP-NEXT: bx lr
|
||||
entry:
|
||||
|
|
@ -812,7 +812,7 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_ord_v4f32(<4 x float> %src, float %src2
|
|||
; CHECK-MVEFP-NEXT: vdup.32 q1, r0
|
||||
; CHECK-MVEFP-NEXT: vcmp.f32 le, q1, q0
|
||||
; CHECK-MVEFP-NEXT: vpst
|
||||
; CHECK-MVEFP-NEXT: vcmpt.f32 lt, q0, q1
|
||||
; CHECK-MVEFP-NEXT: vcmpt.f32 lt, q0, r0
|
||||
; CHECK-MVEFP-NEXT: vmrs r0, p0
|
||||
; CHECK-MVEFP-NEXT: eors r0, r1
|
||||
; CHECK-MVEFP-NEXT: vmsr p0, r0
|
||||
|
|
@ -877,7 +877,7 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_uno_v4f32(<4 x float> %src, float %src2
|
|||
; CHECK-MVEFP-NEXT: vdup.32 q1, r0
|
||||
; CHECK-MVEFP-NEXT: vcmp.f32 le, q1, q0
|
||||
; CHECK-MVEFP-NEXT: vpst
|
||||
; CHECK-MVEFP-NEXT: vcmpt.f32 lt, q0, q1
|
||||
; CHECK-MVEFP-NEXT: vcmpt.f32 lt, q0, r0
|
||||
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
|
||||
; CHECK-MVEFP-NEXT: bx lr
|
||||
entry:
|
||||
|
|
@ -1238,7 +1238,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_one_v8f16(<8 x half> %src, half* %src2p,
|
|||
; CHECK-MVEFP-NEXT: vdup.16 q3, r0
|
||||
; CHECK-MVEFP-NEXT: vcmp.f16 le, q3, q0
|
||||
; CHECK-MVEFP-NEXT: vpst
|
||||
; CHECK-MVEFP-NEXT: vcmpt.f16 le, q0, q3
|
||||
; CHECK-MVEFP-NEXT: vcmpt.f16 le, q0, r0
|
||||
; CHECK-MVEFP-NEXT: vmrs r0, p0
|
||||
; CHECK-MVEFP-NEXT: eors r0, r1
|
||||
; CHECK-MVEFP-NEXT: vmsr p0, r0
|
||||
|
|
@ -2112,7 +2112,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ueq_v8f16(<8 x half> %src, half* %src2p,
|
|||
; CHECK-MVEFP-NEXT: vdup.16 q3, r0
|
||||
; CHECK-MVEFP-NEXT: vcmp.f16 le, q3, q0
|
||||
; CHECK-MVEFP-NEXT: vpst
|
||||
; CHECK-MVEFP-NEXT: vcmpt.f16 le, q0, q3
|
||||
; CHECK-MVEFP-NEXT: vcmpt.f16 le, q0, r0
|
||||
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
|
||||
; CHECK-MVEFP-NEXT: bx lr
|
||||
entry:
|
||||
|
|
@ -3154,7 +3154,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_ord_v8f16(<8 x half> %src, half* %src2p,
|
|||
; CHECK-MVEFP-NEXT: vdup.16 q3, r0
|
||||
; CHECK-MVEFP-NEXT: vcmp.f16 le, q3, q0
|
||||
; CHECK-MVEFP-NEXT: vpst
|
||||
; CHECK-MVEFP-NEXT: vcmpt.f16 lt, q0, q3
|
||||
; CHECK-MVEFP-NEXT: vcmpt.f16 lt, q0, r0
|
||||
; CHECK-MVEFP-NEXT: vmrs r0, p0
|
||||
; CHECK-MVEFP-NEXT: eors r0, r1
|
||||
; CHECK-MVEFP-NEXT: vmsr p0, r0
|
||||
|
|
@ -3330,7 +3330,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_uno_v8f16(<8 x half> %src, half* %src2p,
|
|||
; CHECK-MVEFP-NEXT: vdup.16 q3, r0
|
||||
; CHECK-MVEFP-NEXT: vcmp.f16 le, q3, q0
|
||||
; CHECK-MVEFP-NEXT: vpst
|
||||
; CHECK-MVEFP-NEXT: vcmpt.f16 lt, q0, q3
|
||||
; CHECK-MVEFP-NEXT: vcmpt.f16 lt, q0, r0
|
||||
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
|
||||
; CHECK-MVEFP-NEXT: bx lr
|
||||
entry:
|
||||
|
|
|
|||
Loading…
Reference in New Issue