forked from OSchip/llvm-project
[RISCV] Fix crash in decoding instruction with unknown floating point rounding mode
Summary: Instead of crashing in printFRMArg, decode and warn about invalid instruction. This bug was uncovered by a LLVM MC Disassembler Protocol Buffer Fuzzer for the RISC-V assembly language. Reviewers: asb Reviewed By: asb Subscribers: rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, mgrang, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, asb Differential Revision: https://reviews.llvm.org/D51705 llvm-svn: 341691
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@ -11,6 +11,7 @@
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//
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/RISCVBaseInfo.h"
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#include "MCTargetDesc/RISCVMCTargetDesc.h"
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#include "MCTargetDesc/RISCVMCTargetDesc.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCDisassembler/MCDisassembler.h"
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#include "llvm/MC/MCDisassembler/MCDisassembler.h"
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@ -243,6 +244,17 @@ static DecodeStatus decodeCLUIImmOperand(MCInst &Inst, uint64_t Imm,
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return MCDisassembler::Success;
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return MCDisassembler::Success;
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}
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}
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static DecodeStatus decodeFRMArg(MCInst &Inst, uint64_t Imm,
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int64_t Address,
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const void *Decoder) {
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assert(isUInt<3>(Imm) && "Invalid immediate");
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if (!llvm::RISCVFPRndMode::isValidRoundingMode(Imm))
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return MCDisassembler::Fail;
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Inst.addOperand(MCOperand::createImm(Imm));
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return MCDisassembler::Success;
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}
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#include "RISCVGenDisassemblerTables.inc"
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#include "RISCVGenDisassemblerTables.inc"
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DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
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DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
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@ -104,6 +104,21 @@ inline static RoundingMode stringToRoundingMode(StringRef Str) {
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.Case("dyn", RISCVFPRndMode::DYN)
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.Case("dyn", RISCVFPRndMode::DYN)
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.Default(RISCVFPRndMode::Invalid);
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.Default(RISCVFPRndMode::Invalid);
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}
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}
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inline static bool isValidRoundingMode(unsigned Mode) {
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switch (Mode) {
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default:
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return false;
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case RISCVFPRndMode::RNE:
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case RISCVFPRndMode::RTZ:
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case RISCVFPRndMode::RDN:
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case RISCVFPRndMode::RUP:
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case RISCVFPRndMode::RMM:
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case RISCVFPRndMode::DYN:
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return true;
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}
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}
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} // namespace RISCVFPRndMode
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} // namespace RISCVFPRndMode
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} // namespace llvm
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} // namespace llvm
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@ -27,7 +27,7 @@ def FRMArg : AsmOperandClass {
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def frmarg : Operand<XLenVT> {
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def frmarg : Operand<XLenVT> {
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let ParserMatchClass = FRMArg;
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let ParserMatchClass = FRMArg;
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let PrintMethod = "printFRMArg";
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let PrintMethod = "printFRMArg";
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let DecoderMethod = "decodeUImmOperand<3>";
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let DecoderMethod = "decodeFRMArg";
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}
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}
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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@ -0,0 +1,9 @@
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# RUN: not llvm-mc -disassemble -triple=riscv32 -mattr=+f,+d < %s 2>&1 | FileCheck %s
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# RUN: not llvm-mc -disassemble -triple=riscv64 -mattr=+f,+d < %s 2>&1 | FileCheck %s
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#
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# Test generated by a LLVM MC Disassembler Protocol Buffer Fuzzer
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# for the RISC-V assembly language.
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# This decodes as fadd.s ft0, ft0, ft0 with unknown floating point rounding mode
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[0x53 0x50 0x00 0x00]
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# CHECK: warning: invalid instruction encoding
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