forked from OSchip/llvm-project
parent
d6c80dec76
commit
b2e4d84305
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@ -2235,7 +2235,7 @@ bool ilp_ls_rr_sort::isReady(SUnit *SU, unsigned CurCycle) const {
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return true;
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}
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bool canEnableCoaelscing(SUnit *SU) {
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static bool canEnableCoalescing(SUnit *SU) {
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unsigned Opc = SU->getNode() ? SU->getNode()->getOpcode() : 0;
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if (Opc == ISD::TokenFactor || Opc == ISD::CopyToReg)
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// CopyToReg should be close to its uses to facilitate coalescing and
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@ -2278,8 +2278,8 @@ bool ilp_ls_rr_sort::operator()(SUnit *left, SUnit *right) const {
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}
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if (!DisableSchedRegPressure && (LPDiff > 0 || RPDiff > 0)) {
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bool LReduce = canEnableCoaelscing(left);
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bool RReduce = canEnableCoaelscing(right);
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bool LReduce = canEnableCoalescing(left);
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bool RReduce = canEnableCoalescing(right);
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DEBUG(if (LReduce != RReduce) ++FactorCount[FactPressureDiff]);
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if (LReduce && !RReduce) return false;
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if (RReduce && !LReduce) return true;
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