forked from OSchip/llvm-project
[SimplifyCFG] Range reduce switches
If a switch is sparse and all the cases (once sorted) are in arithmetic progression, we can extract the common factor out of the switch and create a dense switch. For example:
switch (i) {
case 5: ...
case 9: ...
case 13: ...
case 17: ...
}
can become:
if ( (i - 5) % 4 ) goto default;
switch ((i - 5) / 4) {
case 0: ...
case 1: ...
case 2: ...
case 3: ...
}
or even better:
switch ( ROTR(i - 5, 2) {
case 0: ...
case 1: ...
case 2: ...
case 3: ...
}
The division and remainder operations could be costly so we only do this if the factor is a power of two, and emit a right-rotate instead of a divide/remainder sequence. Dense switches can be lowered significantly better than sparse switches and can even be transformed into lookup tables.
llvm-svn: 277325
This commit is contained in:
James Molloy
parent
9f0546b5a9
commit
b2e436de42
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@ -5038,6 +5038,109 @@ static bool SwitchToLookupTable(SwitchInst *SI, IRBuilder<> &Builder,
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return true;
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}
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static bool isSwitchDense(ArrayRef<int64_t> Values) {
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// See also SelectionDAGBuilder::isDense(), which this function was based on.
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uint64_t Diff = (uint64_t)Values.back() - (uint64_t)Values.front();
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uint64_t Range = Diff + 1;
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uint64_t NumCases = Values.size();
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// 40% is the default density for building a jump table in optsize/minsize mode.
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uint64_t MinDensity = 40;
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return NumCases * 100 >= Range * MinDensity;
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}
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// Try and transform a switch that has "holes" in it to a contiguous sequence
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// of cases.
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//
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// A switch such as: switch(i) {case 5: case 9: case 13: case 17:} can be
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// range-reduced to: switch ((i-5) / 4) {case 0: case 1: case 2: case 3:}.
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//
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// This converts a sparse switch into a dense switch which allows better
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// lowering and could also allow transforming into a lookup table.
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static bool ReduceSwitchRange(SwitchInst *SI, IRBuilder<> &Builder,
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const DataLayout &DL,
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const TargetTransformInfo &TTI) {
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auto *CondTy = cast<IntegerType>(SI->getCondition()->getType());
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if (CondTy->getIntegerBitWidth() > 64 ||
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!DL.fitsInLegalInteger(CondTy->getIntegerBitWidth()))
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return false;
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// Only bother with this optimization if there are more than 3 switch cases;
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// SDAG will only bother creating jump tables for 4 or more cases.
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if (SI->getNumCases() < 4)
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return false;
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// This transform is agnostic to the signedness of the input or case values. We
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// can treat the case values as signed or unsigned. We can optimize more common
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// cases such as a sequence crossing zero {-4,0,4,8} if we interpret case values
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// as signed.
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SmallVector<int64_t,4> Values;
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for (auto &C : SI->cases())
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Values.push_back(C.getCaseValue()->getValue().getSExtValue());
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std::sort(Values.begin(), Values.end());
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// If the switch is already dense, there's nothing useful to do here.
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if (isSwitchDense(Values))
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return false;
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// First, transform the values such that they start at zero and ascend.
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int64_t Base = Values[0];
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for (auto &V : Values)
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V -= Base;
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// Now we have signed numbers that have been shifted so that, given enough
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// precision, there are no negative values. Since the rest of the transform
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// is bitwise only, we switch now to an unsigned representation.
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uint64_t GCD = 0;
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for (auto &V : Values)
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GCD = llvm::GreatestCommonDivisor64(GCD, (uint64_t)V);
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// This transform can be done speculatively because it is so cheap - it results
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// in a single rotate operation being inserted. This can only happen if the
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// factor extracted is a power of 2.
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// FIXME: If the GCD is an odd number we can multiply by the multiplicative
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// inverse of GCD and then perform this transform.
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// FIXME: It's possible that optimizing a switch on powers of two might also
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// be beneficial - flag values are often powers of two and we could use a CLZ
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// as the key function.
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if (GCD <= 1 || !llvm::isPowerOf2_64(GCD))
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// No common divisor found or too expensive to compute key function.
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return false;
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unsigned Shift = llvm::Log2_64(GCD);
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for (auto &V : Values)
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V = (int64_t)((uint64_t)V >> Shift);
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if (!isSwitchDense(Values))
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// Transform didn't create a dense switch.
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return false;
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// The obvious transform is to shift the switch condition right and emit a
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// check that the condition actually cleanly divided by GCD, i.e.
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// C & (1 << Shift - 1) == 0
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// inserting a new CFG edge to handle the case where it didn't divide cleanly.
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//
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// A cheaper way of doing this is a simple ROTR(C, Shift). This performs the
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// shift and puts the shifted-off bits in the uppermost bits. If any of these
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// are nonzero then the switch condition will be very large and will hit the
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// default case.
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auto *Ty = cast<IntegerType>(SI->getCondition()->getType());
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Builder.SetInsertPoint(SI);
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auto *ShiftC = ConstantInt::get(Ty, Shift);
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auto *Sub = Builder.CreateSub(SI->getCondition(), ConstantInt::get(Ty, Base));
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auto *Rot = Builder.CreateOr(Builder.CreateLShr(Sub, ShiftC),
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Builder.CreateShl(Sub, Ty->getBitWidth() - Shift));
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SI->replaceUsesOfWith(SI->getCondition(), Rot);
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for (auto &C : SI->cases()) {
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auto *Orig = C.getCaseValue();
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auto Sub = Orig->getValue() - APInt(Ty->getBitWidth(), Base);
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SI->replaceUsesOfWith(Orig,
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ConstantInt::get(Ty, Sub.lshr(ShiftC->getValue())));
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}
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return true;
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}
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bool SimplifyCFGOpt::SimplifySwitch(SwitchInst *SI, IRBuilder<> &Builder) {
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BasicBlock *BB = SI->getParent();
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@ -5081,6 +5184,9 @@ bool SimplifyCFGOpt::SimplifySwitch(SwitchInst *SI, IRBuilder<> &Builder) {
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if (SwitchToLookupTable(SI, Builder, DL, TTI))
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return SimplifyCFG(BB, TTI, BonusInstThreshold, AC) | true;
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if (ReduceSwitchRange(SI, Builder, DL, TTI))
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return SimplifyCFG(BB, TTI, BonusInstThreshold, AC) | true;
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return false;
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}
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@ -0,0 +1,195 @@
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; RUN: opt < %s -simplifycfg -S | FileCheck %s
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target datalayout = "e-n32"
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; CHECK-LABEL: @test1
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; CHECK: %1 = sub i32 %a, 97
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; CHECK: %2 = lshr i32 %1, 2
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; CHECK: %3 = shl i32 %1, 30
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; CHECK: %4 = or i32 %2, %3
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; CHECK: switch i32 %4, label %def [
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; CHECK: i32 0, label %one
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; CHECK: i32 1, label %two
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; CHECK: i32 2, label %three
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; CHECK: ]
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define i32 @test1(i32 %a) {
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switch i32 %a, label %def [
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i32 97, label %one
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i32 101, label %two
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i32 105, label %three
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i32 109, label %three
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]
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def:
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ret i32 8867
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one:
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ret i32 11984
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two:
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ret i32 1143
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three:
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ret i32 99783
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}
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; Optimization shouldn't trigger; bitwidth > 64
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; CHECK-LABEL: @test2
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; CHECK: switch i128 %a, label %def
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define i128 @test2(i128 %a) {
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switch i128 %a, label %def [
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i128 97, label %one
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i128 101, label %two
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i128 105, label %three
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i128 109, label %three
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]
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def:
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ret i128 8867
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one:
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ret i128 11984
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two:
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ret i128 1143
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three:
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ret i128 99783
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}
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; Optimization shouldn't trigger; no holes present
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; CHECK-LABEL: @test3
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; CHECK: switch i32 %a, label %def
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define i32 @test3(i32 %a) {
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switch i32 %a, label %def [
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i32 97, label %one
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i32 98, label %two
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i32 99, label %three
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]
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def:
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ret i32 8867
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one:
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ret i32 11984
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two:
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ret i32 1143
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three:
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ret i32 99783
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}
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; Optimization shouldn't trigger; not an arithmetic progression
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; CHECK-LABEL: @test4
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; CHECK: switch i32 %a, label %def
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define i32 @test4(i32 %a) {
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switch i32 %a, label %def [
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i32 97, label %one
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i32 102, label %two
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i32 105, label %three
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i32 109, label %three
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]
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def:
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ret i32 8867
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one:
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ret i32 11984
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two:
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ret i32 1143
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three:
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ret i32 99783
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}
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; Optimization shouldn't trigger; not a power of two
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; CHECK-LABEL: @test5
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; CHECK: switch i32 %a, label %def
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define i32 @test5(i32 %a) {
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switch i32 %a, label %def [
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i32 97, label %one
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i32 102, label %two
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i32 107, label %three
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i32 112, label %three
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]
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def:
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ret i32 8867
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one:
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ret i32 11984
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two:
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ret i32 1143
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three:
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ret i32 99783
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}
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; CHECK-LABEL: @test6
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; CHECK: %1 = sub i32 %a, -109
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; CHECK: %2 = lshr i32 %1, 2
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; CHECK: %3 = shl i32 %1, 30
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; CHECK: %4 = or i32 %2, %3
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; CHECK: switch i32 %4, label %def [
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define i32 @test6(i32 %a) optsize {
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switch i32 %a, label %def [
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i32 -97, label %one
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i32 -101, label %two
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i32 -105, label %three
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i32 -109, label %three
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]
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def:
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ret i32 8867
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one:
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ret i32 11984
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two:
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ret i32 1143
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three:
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ret i32 99783
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}
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; CHECK-LABEL: @test7
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; CHECK: %1 = sub i8 %a, -36
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; CHECK: %2 = lshr i8 %1, 2
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; CHECK: %3 = shl i8 %1, 6
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; CHECK: %4 = or i8 %2, %3
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; CHECK: switch.tableidx = {{.*}} %4
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define i8 @test7(i8 %a) optsize {
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switch i8 %a, label %def [
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i8 220, label %one
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i8 224, label %two
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i8 228, label %three
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i8 232, label %three
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]
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def:
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ret i8 8867
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one:
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ret i8 11984
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two:
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ret i8 1143
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three:
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ret i8 99783
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}
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; CHECK-LABEL: @test8
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; CHECK: %1 = sub i32 %a, 97
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; CHECK: %2 = lshr i32 %1, 2
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; CHECK: %3 = shl i32 %1, 30
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; CHECK: %4 = or i32 %2, %3
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; CHECK: switch i32 %4, label %def [
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define i32 @test8(i32 %a) optsize {
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switch i32 %a, label %def [
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i32 97, label %one
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i32 101, label %two
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i32 105, label %three
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i32 113, label %three
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]
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def:
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ret i32 8867
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one:
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ret i32 11984
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two:
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ret i32 1143
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three:
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ret i32 99783
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}
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