maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

[Hexagon] SETEQ and SETNE are valid integer condition codes 

llvm-svn: 323452
This commit is contained in:
Krzysztof Parzyszek 2018-01-25 18:07:27 +00:00
parent d22f07bbbe
commit b2c458e648
2 changed files with 23 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
View File

@ -1289,7 +1289,8 @@ SDValue HexagonTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
EVT RHSVT = RHS.getValueType(); EVT RHSVT = RHS.getValueType();
if (LHSVT == MVT::v2i16) { if (LHSVT == MVT::v2i16) {
assert(ISD::isSignedIntSetCC(CC) || ISD::isUnsignedIntSetCC(CC)); assert(CC == ISD::SETEQ || CC == ISD::SETNE ||
ISD::isSignedIntSetCC(CC) || ISD::isUnsignedIntSetCC(CC));
unsigned ExtOpc = ISD::isSignedIntSetCC(CC) ? ISD::SIGN_EXTEND unsigned ExtOpc = ISD::isSignedIntSetCC(CC) ? ISD::SIGN_EXTEND
: ISD::ZERO_EXTEND; : ISD::ZERO_EXTEND;
SDValue LX = DAG.getNode(ExtOpc, dl, MVT::v2i32, LHS); SDValue LX = DAG.getNode(ExtOpc, dl, MVT::v2i32, LHS);

21
llvm/test/CodeGen/Hexagon/vect/setcc-v2i32.ll Normal file
View File

@ -0,0 +1,21 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
; REQUIRES: asserts
; Check that this testcase doesn't crash.
; CHECK: vcmpw.eq
target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
target triple = "hexagon"
define i32 @fred(<2 x i16>* %a0) #0 {
b1:
%v2 = load <2 x i16>, <2 x i16>* %a0, align 2
%v3 = icmp eq <2 x i16> %v2, zeroinitializer
%v4 = zext <2 x i1> %v3 to <2 x i16>
%v5 = extractelement <2 x i16> %v4, i32 1
%v8 = icmp ne i16 %v5, 1
%v9 = zext i1 %v8 to i32
ret i32 %v9
}
attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx-length64b,+hvxv60" }