forked from OSchip/llvm-project
[X86] Add support for -mvzeroupper and -mno-vzeroupper to match gcc
-mvzeroupper will force the vzeroupper insertion pass to run on CPUs that normally wouldn't. -mno-vzeroupper disables it on CPUs where it normally runs. To support this with the default feature handling in clang, we need a vzeroupper feature flag in X86.td. Since this flag has the opposite polarity of the fast-partial-ymm-or-zmm-write we used to use to disable the pass, we now need to add this new flag to every CPU except KNL/KNM and BTVER2 to keep identical behavior. Remove -fast-partial-ymm-or-zmm-write which is no longer used. Differential Revision: https://reviews.llvm.org/D69786
This commit is contained in:
Craig Topper
parent
6ff439b57f
commit
b2b6a54f84
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@ -93,6 +93,10 @@ New Compiler Flags
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Clang. Setting the version to zero causes Clang to leave ``__GNUC__`` and
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other GNU-namespaced macros, such as ``__GXX_WEAK__``, undefined.
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- vzeroupper insertion on X86 targets can now be disabled with -mno-vzeroupper.
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You can also force vzeroupper insertion to be used on CPUs that normally
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wouldn't with -mvzeroupper.
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Deprecated Compiler Flags
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-------------------------
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@ -3135,6 +3135,8 @@ def mshstk : Flag<["-"], "mshstk">, Group<m_x86_Features_Group>;
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def mno_shstk : Flag<["-"], "mno-shstk">, Group<m_x86_Features_Group>;
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def mretpoline_external_thunk : Flag<["-"], "mretpoline-external-thunk">, Group<m_x86_Features_Group>;
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def mno_retpoline_external_thunk : Flag<["-"], "mno-retpoline-external-thunk">, Group<m_x86_Features_Group>;
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def mvzeroupper : Flag<["-"], "mvzeroupper">, Group<m_x86_Features_Group>;
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def mno_vzeroupper : Flag<["-"], "mno-vzeroupper">, Group<m_x86_Features_Group>;
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// These are legacy user-facing driver-level option spellings. They are always
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// aliases for options that are spelled using the more common Unix / GNU flag
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@ -193,3 +193,8 @@
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// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mno-enqcmd %s -### -o %t.o 2>&1 | FileCheck --check-prefix=NO-ENQCMD %s
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// ENQCMD: "-target-feature" "+enqcmd"
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// NO-ENQCMD: "-target-feature" "-enqcmd"
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// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mvzeroupper %s -### -o %t.o 2>&1 | FileCheck --check-prefix=VZEROUPPER %s
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// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mno-vzeroupper %s -### -o %t.o 2>&1 | FileCheck --check-prefix=NO-VZEROUPPER %s
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// VZEROUPPER: "-target-feature" "+vzeroupper"
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// NO-VZEROUPPER: "-target-feature" "-vzeroupper"
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@ -134,6 +134,13 @@ Changes to the X86 Target
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Intel CPUs. This tries to limit the use of 512-bit registers which can cause a
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decrease in CPU frequency on these CPUs. This can be re-enabled by passing
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-mprefer-vector-width=512 to clang or passing -mattr=-prefer-256-bit to llc.
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* Deprecated the mpx feature flag for the Intel MPX instructions. There were no
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intrinsics for this feature. This change only this effects the results
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returned by getHostCPUFeatures on CPUs that implement the MPX instructions.
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* The feature flag fast-partial-ymm-or-zmm-write which previously disabled
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vzeroupper insertion has been removed. It has been replaced with a vzeroupper
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feature flag which has the opposite polarity. So -vzeroupper has the same
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effect as +fast-partial-ymm-or-zmm-write.
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Changes to the AMDGPU Target
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-----------------------------
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@ -143,10 +150,6 @@ Changes to the AVR Target
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During this release ...
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* Deprecated the mpx feature flag for the Intel MPX instructions. There were no
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intrinsics for this feature. This change only this effects the results
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returned by getHostCPUFeatures on CPUs that implement the MPX instructions.
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Changes to the WebAssembly Target
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---------------------------------
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@ -304,12 +304,12 @@ def FeatureFastVariableShuffle
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: SubtargetFeature<"fast-variable-shuffle",
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"HasFastVariableShuffle",
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"true", "Shuffles with variable masks are fast">;
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// On some X86 processors, there is no performance hazard to writing only the
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// lower parts of a YMM or ZMM register without clearing the upper part.
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def FeatureFastPartialYMMorZMMWrite
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: SubtargetFeature<"fast-partial-ymm-or-zmm-write",
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"HasFastPartialYMMorZMMWrite",
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"true", "Partial writes to YMM/ZMM registers are fast">;
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// On some X86 processors, a vzeroupper instruction should be inserted after
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// using ymm/zmm registers before executing code that may use SSE instructions.
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def FeatureInsertVZEROUPPER
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: SubtargetFeature<"vzeroupper",
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"InsertVZEROUPPER",
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"true", "Should insert vzeroupper instructions">;
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// FeatureFastScalarFSQRT should be enabled if scalar FSQRT has shorter latency
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// than the corresponding NR code. FeatureFastVectorFSQRT should be enabled if
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// vector FSQRT has higher throughput than the corresponding NR code.
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@ -525,7 +525,8 @@ def ProcessorFeatures {
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FeatureCMPXCHG16B,
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FeaturePOPCNT,
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FeatureLAHFSAHF,
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FeatureMacroFusion];
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FeatureMacroFusion,
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FeatureInsertVZEROUPPER];
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list<SubtargetFeature> NHMSpecificFeatures = [];
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list<SubtargetFeature> NHMFeatures =
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!listconcat(NHMInheritableFeatures, NHMSpecificFeatures);
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@ -705,7 +706,8 @@ def ProcessorFeatures {
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FeatureCMPXCHG16B,
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FeatureMOVBE,
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FeatureSlowTwoMemOps,
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FeatureLAHFSAHF];
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FeatureLAHFSAHF,
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FeatureInsertVZEROUPPER];
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list<SubtargetFeature> AtomSpecificFeatures = [ProcIntelAtom,
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FeatureSlowUAMem16,
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FeatureLEAForSP,
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@ -807,7 +809,6 @@ def ProcessorFeatures {
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FeaturePRFCHW,
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FeaturePreferMaskRegisters,
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FeatureSlowTwoMemOps,
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FeatureFastPartialYMMorZMMWrite,
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FeatureHasFastGather,
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FeatureSlowPMADDWD];
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// TODO Add AVX5124FMAPS/AVX5124VNNIW features
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@ -828,7 +829,8 @@ def ProcessorFeatures {
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FeatureLAHFSAHF,
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FeatureCMOV,
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Feature64Bit,
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FeatureFastScalarShiftMasks];
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FeatureFastScalarShiftMasks,
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FeatureInsertVZEROUPPER];
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list<SubtargetFeature> BarcelonaFeatures = BarcelonaInheritableFeatures;
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// Bobcat
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@ -850,7 +852,9 @@ def ProcessorFeatures {
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FeatureFast15ByteNOP,
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FeatureFastScalarShiftMasks,
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FeatureFastVectorShiftMasks];
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list<SubtargetFeature> BtVer1Features = BtVer1InheritableFeatures;
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list<SubtargetFeature> BtVer1SpecificFeatures = [FeatureInsertVZEROUPPER];
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list<SubtargetFeature> BtVer1Features =
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!listconcat(BtVer1InheritableFeatures, BtVer1SpecificFeatures);
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// Jaguar
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list<SubtargetFeature> BtVer2AdditionalFeatures = [FeatureAVX,
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@ -863,7 +867,6 @@ def ProcessorFeatures {
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FeatureXSAVEOPT];
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list<SubtargetFeature> BtVer2SpecificFeatures = [FeatureFastLZCNT,
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FeatureFastBEXTR,
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FeatureFastPartialYMMorZMMWrite,
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FeatureFastHorizontalOps];
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list<SubtargetFeature> BtVer2InheritableFeatures =
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!listconcat(BtVer1InheritableFeatures, BtVer2AdditionalFeatures);
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@ -891,7 +894,8 @@ def ProcessorFeatures {
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FeatureLAHFSAHF,
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FeatureFast11ByteNOP,
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FeatureFastScalarShiftMasks,
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FeatureBranchFusion];
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FeatureBranchFusion,
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FeatureInsertVZEROUPPER];
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list<SubtargetFeature> BdVer1Features = BdVer1InheritableFeatures;
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// PileDriver
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@ -954,6 +958,7 @@ def ProcessorFeatures {
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FeatureSHA,
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FeatureSSE4A,
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FeatureSlowSHLD,
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FeatureInsertVZEROUPPER,
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FeatureX87,
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FeatureXSAVE,
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FeatureXSAVEC,
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@ -976,28 +981,32 @@ class Proc<string Name, list<SubtargetFeature> Features>
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// NOTE: CMPXCHG8B is here for legacy compatbility so that it is only disabled
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// if i386/i486 is specifically requested.
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def : Proc<"generic", [FeatureX87, FeatureSlowUAMem16,
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FeatureCMPXCHG8B]>;
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def : Proc<"i386", [FeatureX87, FeatureSlowUAMem16]>;
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def : Proc<"i486", [FeatureX87, FeatureSlowUAMem16]>;
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FeatureCMPXCHG8B, FeatureInsertVZEROUPPER]>;
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def : Proc<"i386", [FeatureX87, FeatureSlowUAMem16,
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FeatureInsertVZEROUPPER]>;
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def : Proc<"i486", [FeatureX87, FeatureSlowUAMem16,
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FeatureInsertVZEROUPPER]>;
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def : Proc<"i586", [FeatureX87, FeatureSlowUAMem16,
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FeatureCMPXCHG8B]>;
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FeatureCMPXCHG8B, FeatureInsertVZEROUPPER]>;
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def : Proc<"pentium", [FeatureX87, FeatureSlowUAMem16,
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FeatureCMPXCHG8B]>;
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FeatureCMPXCHG8B, FeatureInsertVZEROUPPER]>;
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def : Proc<"pentium-mmx", [FeatureX87, FeatureSlowUAMem16,
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FeatureCMPXCHG8B, FeatureMMX]>;
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FeatureCMPXCHG8B, FeatureMMX,
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FeatureInsertVZEROUPPER]>;
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def : Proc<"i686", [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
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FeatureCMOV]>;
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FeatureCMOV, FeatureInsertVZEROUPPER]>;
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def : Proc<"pentiumpro", [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
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FeatureCMOV, FeatureNOPL]>;
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FeatureCMOV, FeatureNOPL, FeatureInsertVZEROUPPER]>;
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def : Proc<"pentium2", [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
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FeatureMMX, FeatureCMOV, FeatureFXSR,
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FeatureNOPL]>;
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FeatureNOPL, FeatureInsertVZEROUPPER]>;
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foreach P = ["pentium3", "pentium3m"] in {
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def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,FeatureMMX,
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FeatureSSE1, FeatureFXSR, FeatureNOPL, FeatureCMOV]>;
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FeatureSSE1, FeatureFXSR, FeatureNOPL, FeatureCMOV,
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FeatureInsertVZEROUPPER]>;
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}
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// Enable the PostRAScheduler for SSE2 and SSE3 class cpus.
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@ -1013,29 +1022,29 @@ foreach P = ["pentium3", "pentium3m"] in {
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def : ProcessorModel<"pentium-m", GenericPostRAModel,
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[FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
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FeatureMMX, FeatureSSE2, FeatureFXSR, FeatureNOPL,
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FeatureCMOV]>;
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FeatureCMOV, FeatureInsertVZEROUPPER]>;
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foreach P = ["pentium4", "pentium4m"] in {
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def : ProcessorModel<P, GenericPostRAModel,
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[FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
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FeatureMMX, FeatureSSE2, FeatureFXSR, FeatureNOPL,
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FeatureCMOV]>;
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FeatureCMOV, FeatureInsertVZEROUPPER]>;
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}
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// Intel Quark.
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def : Proc<"lakemont", []>;
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def : Proc<"lakemont", [FeatureInsertVZEROUPPER]>;
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// Intel Core Duo.
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def : ProcessorModel<"yonah", SandyBridgeModel,
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[FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
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FeatureMMX, FeatureSSE3, FeatureFXSR, FeatureNOPL,
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FeatureCMOV]>;
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FeatureCMOV, FeatureInsertVZEROUPPER]>;
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// NetBurst.
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def : ProcessorModel<"prescott", GenericPostRAModel,
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[FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
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FeatureMMX, FeatureSSE3, FeatureFXSR, FeatureNOPL,
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FeatureCMOV]>;
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FeatureCMOV, FeatureInsertVZEROUPPER]>;
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def : ProcessorModel<"nocona", GenericPostRAModel, [
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FeatureX87,
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FeatureSlowUAMem16,
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@ -1046,7 +1055,8 @@ def : ProcessorModel<"nocona", GenericPostRAModel, [
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FeatureFXSR,
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FeatureNOPL,
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Feature64Bit,
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FeatureCMPXCHG16B
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FeatureCMPXCHG16B,
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FeatureInsertVZEROUPPER
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]>;
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// Intel Core 2 Solo/Duo.
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@ -1062,7 +1072,8 @@ def : ProcessorModel<"core2", SandyBridgeModel, [
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Feature64Bit,
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FeatureCMPXCHG16B,
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FeatureLAHFSAHF,
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FeatureMacroFusion
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FeatureMacroFusion,
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FeatureInsertVZEROUPPER
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]>;
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def : ProcessorModel<"penryn", SandyBridgeModel, [
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FeatureX87,
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@ -1076,7 +1087,8 @@ def : ProcessorModel<"penryn", SandyBridgeModel, [
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Feature64Bit,
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FeatureCMPXCHG16B,
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FeatureLAHFSAHF,
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FeatureMacroFusion
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FeatureMacroFusion,
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FeatureInsertVZEROUPPER
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]>;
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// Atom CPUs.
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@ -1143,35 +1155,36 @@ def : ProcessorModel<"tigerlake", SkylakeServerModel,
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// AMD CPUs.
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def : Proc<"k6", [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
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FeatureMMX]>;
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FeatureMMX, FeatureInsertVZEROUPPER]>;
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def : Proc<"k6-2", [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
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Feature3DNow]>;
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Feature3DNow, FeatureInsertVZEROUPPER]>;
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def : Proc<"k6-3", [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
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Feature3DNow]>;
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Feature3DNow, FeatureInsertVZEROUPPER]>;
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foreach P = ["athlon", "athlon-tbird"] in {
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def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B, FeatureCMOV,
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Feature3DNowA, FeatureNOPL, FeatureSlowSHLD]>;
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Feature3DNowA, FeatureNOPL, FeatureSlowSHLD,
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FeatureInsertVZEROUPPER]>;
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}
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foreach P = ["athlon-4", "athlon-xp", "athlon-mp"] in {
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def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B, FeatureCMOV,
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FeatureSSE1, Feature3DNowA, FeatureFXSR, FeatureNOPL,
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FeatureSlowSHLD]>;
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FeatureSlowSHLD, FeatureInsertVZEROUPPER]>;
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}
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foreach P = ["k8", "opteron", "athlon64", "athlon-fx"] in {
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def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
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FeatureSSE2, Feature3DNowA, FeatureFXSR, FeatureNOPL,
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Feature64Bit, FeatureSlowSHLD, FeatureCMOV,
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FeatureFastScalarShiftMasks]>;
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FeatureFastScalarShiftMasks, FeatureInsertVZEROUPPER]>;
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}
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foreach P = ["k8-sse3", "opteron-sse3", "athlon64-sse3"] in {
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def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B, FeatureSSE3,
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Feature3DNowA, FeatureFXSR, FeatureNOPL, FeatureCMPXCHG16B,
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FeatureSlowSHLD, FeatureCMOV, Feature64Bit,
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FeatureFastScalarShiftMasks]>;
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FeatureFastScalarShiftMasks, FeatureInsertVZEROUPPER]>;
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}
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foreach P = ["amdfam10", "barcelona"] in {
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@ -1196,14 +1209,17 @@ def : ProcessorModel<"znver1", Znver1Model, ProcessorFeatures.ZNFeatures>;
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def : ProcessorModel<"znver2", Znver1Model, ProcessorFeatures.ZN2Features>;
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def : Proc<"geode", [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
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Feature3DNowA]>;
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Feature3DNowA, FeatureInsertVZEROUPPER]>;
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def : Proc<"winchip-c6", [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>;
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def : Proc<"winchip2", [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>;
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def : Proc<"c3", [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>;
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def : Proc<"winchip-c6", [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
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FeatureInsertVZEROUPPER]>;
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def : Proc<"winchip2", [FeatureX87, FeatureSlowUAMem16, Feature3DNow,
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FeatureInsertVZEROUPPER]>;
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def : Proc<"c3", [FeatureX87, FeatureSlowUAMem16, Feature3DNow,
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FeatureInsertVZEROUPPER]>;
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def : Proc<"c3-2", [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
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FeatureMMX, FeatureSSE1, FeatureFXSR,
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FeatureCMOV]>;
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FeatureCMOV, FeatureInsertVZEROUPPER]>;
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// We also provide a generic 64-bit specific x86 processor model which tries to
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// be good for modern chips without enabling instruction set encodings past the
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@ -1226,7 +1242,8 @@ def : ProcessorModel<"x86-64", SandyBridgeModel, [
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Feature64Bit,
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FeatureSlow3OpsLEA,
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FeatureSlowIncDec,
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FeatureMacroFusion
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FeatureMacroFusion,
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FeatureInsertVZEROUPPER
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]>;
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//===----------------------------------------------------------------------===//
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@ -256,9 +256,9 @@ protected:
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/// mask over multiple fixed shuffles.
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bool HasFastVariableShuffle = false;
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/// True if there is no performance penalty to writing only the lower parts
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/// of a YMM or ZMM register without clearing the upper part.
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bool HasFastPartialYMMorZMMWrite = false;
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/// True if vzeroupper instructions should be inserted after code that uses
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/// ymm or zmm registers.
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bool InsertVZEROUPPER = false;
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/// True if there is no performance penalty for writing NOPs with up to
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/// 11 bytes.
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@ -658,9 +658,7 @@ public:
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bool hasFastVariableShuffle() const {
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return HasFastVariableShuffle;
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}
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bool hasFastPartialYMMorZMMWrite() const {
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return HasFastPartialYMMorZMMWrite;
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}
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bool insertVZEROUPPER() const { return InsertVZEROUPPER; }
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bool hasFastGather() const { return HasFastGather; }
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bool hasFastScalarFSQRT() const { return HasFastScalarFSQRT; }
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bool hasFastVectorFSQRT() const { return HasFastVectorFSQRT; }
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@ -51,7 +51,6 @@ class X86TTIImpl : public BasicTTIImplBase<X86TTIImpl> {
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X86::FeatureFastBEXTR,
|
||||
X86::FeatureFastHorizontalOps,
|
||||
X86::FeatureFastLZCNT,
|
||||
X86::FeatureFastPartialYMMorZMMWrite,
|
||||
X86::FeatureFastScalarFSQRT,
|
||||
X86::FeatureFastSHLDRotate,
|
||||
X86::FeatureFastScalarShiftMasks,
|
||||
|
|
@ -78,6 +77,7 @@ class X86TTIImpl : public BasicTTIImplBase<X86TTIImpl> {
|
|||
X86::FeatureSlowTwoMemOps,
|
||||
X86::FeatureSlowUAMem16,
|
||||
X86::FeaturePreferMaskRegisters,
|
||||
X86::FeatureInsertVZEROUPPER,
|
||||
|
||||
// Perf-tuning flags.
|
||||
X86::FeatureHasFastGather,
|
||||
|
|
|
|||
|
|
@ -279,7 +279,7 @@ void VZeroUpperInserter::processBasicBlock(MachineBasicBlock &MBB) {
|
|||
/// function calls.
|
||||
bool VZeroUpperInserter::runOnMachineFunction(MachineFunction &MF) {
|
||||
const X86Subtarget &ST = MF.getSubtarget<X86Subtarget>();
|
||||
if (!ST.hasAVX() || ST.hasFastPartialYMMorZMMWrite())
|
||||
if (!ST.hasAVX() || !ST.insertVZEROUPPER())
|
||||
return false;
|
||||
TII = ST.getInstrInfo();
|
||||
MachineRegisterInfo &MRI = MF.getRegInfo();
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc < %s -x86-use-vzeroupper -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=VZ --check-prefix=AVX
|
||||
; RUN: llc < %s -x86-use-vzeroupper -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefix=ALL --check-prefix=VZ --check-prefix=AVX512
|
||||
; RUN: llc < %s -x86-use-vzeroupper -mtriple=x86_64-unknown-unknown -mattr=+avx,+fast-partial-ymm-or-zmm-write | FileCheck %s --check-prefix=ALL --check-prefix=NO-VZ --check-prefix=FAST-ymm-zmm
|
||||
; RUN: llc < %s -x86-use-vzeroupper -mtriple=x86_64-unknown-unknown -mattr=+avx,-vzeroupper | FileCheck %s --check-prefix=ALL --check-prefix=NO-VZ --check-prefix=DISABLE-VZ
|
||||
; RUN: llc < %s -x86-use-vzeroupper -mtriple=x86_64-unknown-unknown -mcpu=bdver2 | FileCheck %s --check-prefix=ALL --check-prefix=NO-VZ --check-prefix=BDVER2
|
||||
; RUN: llc < %s -x86-use-vzeroupper -mtriple=x86_64-unknown-unknown -mcpu=btver2 | FileCheck %s --check-prefix=ALL --check-prefix=NO-VZ --check-prefix=BTVER2
|
||||
|
||||
|
|
@ -44,18 +44,18 @@ define <8 x float> @test01(<4 x float> %a, <4 x float> %b, <8 x float> %c) nounw
|
|||
; VZ-NEXT: addq $56, %rsp
|
||||
; VZ-NEXT: retq
|
||||
;
|
||||
; FAST-ymm-zmm-LABEL: test01:
|
||||
; FAST-ymm-zmm: # %bb.0:
|
||||
; FAST-ymm-zmm-NEXT: subq $56, %rsp
|
||||
; FAST-ymm-zmm-NEXT: vmovups %ymm2, (%rsp) # 32-byte Spill
|
||||
; FAST-ymm-zmm-NEXT: vmovaps {{.*}}(%rip), %xmm0
|
||||
; FAST-ymm-zmm-NEXT: callq do_sse
|
||||
; FAST-ymm-zmm-NEXT: vmovaps %xmm0, {{.*}}(%rip)
|
||||
; FAST-ymm-zmm-NEXT: callq do_sse
|
||||
; FAST-ymm-zmm-NEXT: vmovaps %xmm0, {{.*}}(%rip)
|
||||
; FAST-ymm-zmm-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload
|
||||
; FAST-ymm-zmm-NEXT: addq $56, %rsp
|
||||
; FAST-ymm-zmm-NEXT: retq
|
||||
; DISABLE-VZ-LABEL: test01:
|
||||
; DISABLE-VZ: # %bb.0:
|
||||
; DISABLE-VZ-NEXT: subq $56, %rsp
|
||||
; DISABLE-VZ-NEXT: vmovups %ymm2, (%rsp) # 32-byte Spill
|
||||
; DISABLE-VZ-NEXT: vmovaps {{.*}}(%rip), %xmm0
|
||||
; DISABLE-VZ-NEXT: callq do_sse
|
||||
; DISABLE-VZ-NEXT: vmovaps %xmm0, {{.*}}(%rip)
|
||||
; DISABLE-VZ-NEXT: callq do_sse
|
||||
; DISABLE-VZ-NEXT: vmovaps %xmm0, {{.*}}(%rip)
|
||||
; DISABLE-VZ-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload
|
||||
; DISABLE-VZ-NEXT: addq $56, %rsp
|
||||
; DISABLE-VZ-NEXT: retq
|
||||
;
|
||||
; BDVER2-LABEL: test01:
|
||||
; BDVER2: # %bb.0:
|
||||
|
|
@ -83,6 +83,7 @@ define <8 x float> @test01(<4 x float> %a, <4 x float> %b, <8 x float> %c) nounw
|
|||
; BTVER2-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload
|
||||
; BTVER2-NEXT: addq $56, %rsp
|
||||
; BTVER2-NEXT: retq
|
||||
; DISABLE-VZ # %bb.0:
|
||||
%tmp = load <4 x float>, <4 x float>* @x, align 16
|
||||
%call = tail call <4 x float> @do_sse(<4 x float> %tmp) nounwind
|
||||
store <4 x float> %call, <4 x float>* @x, align 16
|
||||
|
|
@ -100,10 +101,10 @@ define <4 x float> @test02(<8 x float> %a, <8 x float> %b) nounwind {
|
|||
; VZ-NEXT: vzeroupper
|
||||
; VZ-NEXT: jmp do_sse # TAILCALL
|
||||
;
|
||||
; FAST-ymm-zmm-LABEL: test02:
|
||||
; FAST-ymm-zmm: # %bb.0:
|
||||
; FAST-ymm-zmm-NEXT: vaddps %xmm1, %xmm0, %xmm0
|
||||
; FAST-ymm-zmm-NEXT: jmp do_sse # TAILCALL
|
||||
; DISABLE-VZ-LABEL: test02:
|
||||
; DISABLE-VZ: # %bb.0:
|
||||
; DISABLE-VZ-NEXT: vaddps %xmm1, %xmm0, %xmm0
|
||||
; DISABLE-VZ-NEXT: jmp do_sse # TAILCALL
|
||||
;
|
||||
; BDVER2-LABEL: test02:
|
||||
; BDVER2: # %bb.0:
|
||||
|
|
@ -154,34 +155,34 @@ define <4 x float> @test03(<4 x float> %a, <4 x float> %b) nounwind {
|
|||
; VZ-NEXT: popq %rbx
|
||||
; VZ-NEXT: retq
|
||||
;
|
||||
; FAST-ymm-zmm-LABEL: test03:
|
||||
; FAST-ymm-zmm: # %bb.0: # %entry
|
||||
; FAST-ymm-zmm-NEXT: pushq %rbx
|
||||
; FAST-ymm-zmm-NEXT: subq $16, %rsp
|
||||
; FAST-ymm-zmm-NEXT: vaddps %xmm1, %xmm0, %xmm0
|
||||
; FAST-ymm-zmm-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
|
||||
; FAST-ymm-zmm-NEXT: .p2align 4, 0x90
|
||||
; FAST-ymm-zmm-NEXT: .LBB3_1: # %while.cond
|
||||
; FAST-ymm-zmm-NEXT: # =>This Inner Loop Header: Depth=1
|
||||
; FAST-ymm-zmm-NEXT: callq foo
|
||||
; FAST-ymm-zmm-NEXT: testl %eax, %eax
|
||||
; FAST-ymm-zmm-NEXT: jne .LBB3_1
|
||||
; FAST-ymm-zmm-NEXT: # %bb.2: # %for.body.preheader
|
||||
; FAST-ymm-zmm-NEXT: movl $4, %ebx
|
||||
; FAST-ymm-zmm-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
|
||||
; FAST-ymm-zmm-NEXT: .p2align 4, 0x90
|
||||
; FAST-ymm-zmm-NEXT: .LBB3_3: # %for.body
|
||||
; FAST-ymm-zmm-NEXT: # =>This Inner Loop Header: Depth=1
|
||||
; FAST-ymm-zmm-NEXT: callq do_sse
|
||||
; FAST-ymm-zmm-NEXT: callq do_sse
|
||||
; FAST-ymm-zmm-NEXT: vmovaps g+{{.*}}(%rip), %xmm0
|
||||
; FAST-ymm-zmm-NEXT: callq do_sse
|
||||
; FAST-ymm-zmm-NEXT: decl %ebx
|
||||
; FAST-ymm-zmm-NEXT: jne .LBB3_3
|
||||
; FAST-ymm-zmm-NEXT: # %bb.4: # %for.end
|
||||
; FAST-ymm-zmm-NEXT: addq $16, %rsp
|
||||
; FAST-ymm-zmm-NEXT: popq %rbx
|
||||
; FAST-ymm-zmm-NEXT: retq
|
||||
; DISABLE-VZ-LABEL: test03:
|
||||
; DISABLE-VZ: # %bb.0: # %entry
|
||||
; DISABLE-VZ-NEXT: pushq %rbx
|
||||
; DISABLE-VZ-NEXT: subq $16, %rsp
|
||||
; DISABLE-VZ-NEXT: vaddps %xmm1, %xmm0, %xmm0
|
||||
; DISABLE-VZ-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
|
||||
; DISABLE-VZ-NEXT: .p2align 4, 0x90
|
||||
; DISABLE-VZ-NEXT: .LBB3_1: # %while.cond
|
||||
; DISABLE-VZ-NEXT: # =>This Inner Loop Header: Depth=1
|
||||
; DISABLE-VZ-NEXT: callq foo
|
||||
; DISABLE-VZ-NEXT: testl %eax, %eax
|
||||
; DISABLE-VZ-NEXT: jne .LBB3_1
|
||||
; DISABLE-VZ-NEXT: # %bb.2: # %for.body.preheader
|
||||
; DISABLE-VZ-NEXT: movl $4, %ebx
|
||||
; DISABLE-VZ-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
|
||||
; DISABLE-VZ-NEXT: .p2align 4, 0x90
|
||||
; DISABLE-VZ-NEXT: .LBB3_3: # %for.body
|
||||
; DISABLE-VZ-NEXT: # =>This Inner Loop Header: Depth=1
|
||||
; DISABLE-VZ-NEXT: callq do_sse
|
||||
; DISABLE-VZ-NEXT: callq do_sse
|
||||
; DISABLE-VZ-NEXT: vmovaps g+{{.*}}(%rip), %xmm0
|
||||
; DISABLE-VZ-NEXT: callq do_sse
|
||||
; DISABLE-VZ-NEXT: decl %ebx
|
||||
; DISABLE-VZ-NEXT: jne .LBB3_3
|
||||
; DISABLE-VZ-NEXT: # %bb.4: # %for.end
|
||||
; DISABLE-VZ-NEXT: addq $16, %rsp
|
||||
; DISABLE-VZ-NEXT: popq %rbx
|
||||
; DISABLE-VZ-NEXT: retq
|
||||
;
|
||||
; BDVER2-LABEL: test03:
|
||||
; BDVER2: # %bb.0: # %entry
|
||||
|
|
@ -279,15 +280,15 @@ define <4 x float> @test04(<4 x float> %a, <4 x float> %b) nounwind {
|
|||
; VZ-NEXT: vzeroupper
|
||||
; VZ-NEXT: retq
|
||||
;
|
||||
; FAST-ymm-zmm-LABEL: test04:
|
||||
; FAST-ymm-zmm: # %bb.0:
|
||||
; FAST-ymm-zmm-NEXT: pushq %rax
|
||||
; FAST-ymm-zmm-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
|
||||
; FAST-ymm-zmm-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
|
||||
; FAST-ymm-zmm-NEXT: callq do_avx
|
||||
; FAST-ymm-zmm-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
|
||||
; FAST-ymm-zmm-NEXT: popq %rax
|
||||
; FAST-ymm-zmm-NEXT: retq
|
||||
; DISABLE-VZ-LABEL: test04:
|
||||
; DISABLE-VZ: # %bb.0:
|
||||
; DISABLE-VZ-NEXT: pushq %rax
|
||||
; DISABLE-VZ-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
|
||||
; DISABLE-VZ-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
|
||||
; DISABLE-VZ-NEXT: callq do_avx
|
||||
; DISABLE-VZ-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
|
||||
; DISABLE-VZ-NEXT: popq %rax
|
||||
; DISABLE-VZ-NEXT: retq
|
||||
;
|
||||
; BDVER2-LABEL: test04:
|
||||
; BDVER2: # %bb.0:
|
||||
|
|
|
|||
Loading…
Reference in New Issue