forked from OSchip/llvm-project
[LV] Make some tests more robust by adding missing users.
This commit is contained in:
Florian Hahn
parent
0e70dd858e
commit
b2a8eff45c
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@ -11,16 +11,22 @@ target triple = "aarch64--linux-gnu"
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; CHECK-NEXT: [[INDUCTION1:%.*]] = add i64 [[OFFSET_IDX]], 5
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; CHECK-NEXT: [[TMP4:%.*]] = trunc i64 [[INDUCTION]] to i32
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; CHECK-NEXT: [[TMP5:%.*]] = trunc i64 [[INDUCTION1]] to i32
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; CHECK-NEXT: [[GEP0:%.+]] = getelementptr inbounds i32, i32* %dst, i32 [[TMP4]]
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; CHECK-NEXT: [[GEP1:%.+]] = getelementptr inbounds i32, i32* %dst, i32 [[TMP5]]
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; CHECK-NEXT: store i32 0, i32* [[GEP0]], align 4
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; CHECK-NEXT: store i32 0, i32* [[GEP1]], align 4
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; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
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; CHECK: br i1 {{.*}}, label %middle.block, label %vector.body
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;
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define void @non_primary_iv_trunc_free(i64 %n) {
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define void @non_primary_iv_trunc_free(i64 %n, i32* %dst) {
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entry:
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br label %for.body
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for.body:
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%i = phi i64 [ %i.next, %for.body ], [ 0, %entry ]
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%tmp0 = trunc i64 %i to i32
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%gep.dst = getelementptr inbounds i32, i32* %dst, i32 %tmp0
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store i32 0, i32* %gep.dst
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%i.next = add nuw nsw i64 %i, 5
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%cond = icmp slt i64 %i.next, %n
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br i1 %cond, label %for.body, label %for.end
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@ -11,21 +11,25 @@ target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128-p:16:16-p4:32:16"
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; CHECK: load i16, i16*
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; CHECK: load i16, i16 addrspace(4)*
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; CHECK: load i16, i16 addrspace(4)*
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; CHECK: store <2 x i16>
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%rec1445 = type { i16, i16, i16, i16, i16 }
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define void @foo() {
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define void @foo(%rec1445* %a, %rec1445 addrspace(4)* %b, i16* noalias %dst) {
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bb1:
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br label %bb4
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bb4:
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%tmp1 = phi i16 [ undef, %bb1 ], [ %_tmp1013, %bb4 ]
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%tmp2 = phi %rec1445* [ undef, %bb1 ], [ %_tmp1015, %bb4 ]
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%tmp3 = phi %rec1445 addrspace(4)* [ undef, %bb1 ], [ %_tmp1017, %bb4 ]
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%tmp1 = phi i16 [ 0, %bb1 ], [ %_tmp1013, %bb4 ]
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%tmp2 = phi %rec1445* [ %a, %bb1 ], [ %_tmp1015, %bb4 ]
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%tmp3 = phi %rec1445 addrspace(4)* [ %b, %bb1 ], [ %_tmp1017, %bb4 ]
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%0 = getelementptr %rec1445, %rec1445* %tmp2, i16 0, i32 1
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%_tmp987 = load i16, i16* %0, align 1
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%1 = getelementptr %rec1445, %rec1445 addrspace(4)* %tmp3, i32 0, i32 1
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%_tmp993 = load i16, i16 addrspace(4)* %1, align 1
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%add = add i16 %_tmp987, %_tmp993
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%dst.gep = getelementptr inbounds i16, i16* %dst, i16 %tmp1
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store i16 %add, i16* %dst.gep
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%_tmp1013 = add i16 %tmp1, 1
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%_tmp1015 = getelementptr %rec1445, %rec1445* %tmp2, i16 1
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%_tmp1017 = getelementptr %rec1445, %rec1445 addrspace(4)* %tmp3, i32 1
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@ -134,31 +134,6 @@ define void @single_incoming_phi_with_blend_mask(i64 %a, i64 %b) {
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; CHECK: middle.block:
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; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 32, 32
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; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]]
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; CHECK: scalar.ph:
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; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 32, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ]
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; CHECK-NEXT: br label [[LOOP_HEADER:%.*]]
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; CHECK: loop.header:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP_LATCH:%.*]] ]
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; CHECK-NEXT: [[IV_TRUNC:%.*]] = trunc i64 [[IV]] to i16
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; CHECK-NEXT: [[CMP_A:%.*]] = icmp ugt i64 [[IV]], [[A]]
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; CHECK-NEXT: br i1 [[CMP_A]], label [[LOOP_COND:%.*]], label [[LOOP_LATCH]]
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; CHECK: loop.cond:
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; CHECK-NEXT: [[BLEND:%.*]] = phi i16 [ [[IV_TRUNC]], [[LOOP_HEADER]] ]
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; CHECK-NEXT: [[SRC_PTR:%.*]] = getelementptr inbounds [32 x i16], [32 x i16]* @src, i16 0, i16 [[BLEND]]
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; CHECK-NEXT: [[LV:%.*]] = load i16, i16* [[SRC_PTR]], align 1
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; CHECK-NEXT: [[CMP_B:%.*]] = icmp sgt i64 [[IV]], [[A]]
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; CHECK-NEXT: br i1 [[CMP_B]], label [[LOOP_NEXT:%.*]], label [[LOOP_LATCH]]
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; CHECK: loop.next:
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; CHECK-NEXT: br label [[LOOP_LATCH]]
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; CHECK: loop.latch:
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; CHECK-NEXT: [[RES:%.*]] = phi i16 [ 0, [[LOOP_HEADER]] ], [ [[LV]], [[LOOP_COND]] ], [ 1, [[LOOP_NEXT]] ]
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; CHECK-NEXT: [[DST_PTR:%.*]] = getelementptr inbounds [32 x i16], [32 x i16]* @dst, i16 0, i64 [[IV]]
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; CHECK-NEXT: store i16 [[RES]], i16* [[DST_PTR]], align 2
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; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
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; CHECK-NEXT: [[CMP439:%.*]] = icmp ult i64 [[IV]], 31
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; CHECK-NEXT: br i1 [[CMP439]], label [[LOOP_HEADER]], label [[EXIT]], [[LOOP5:!llvm.loop !.*]]
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; CHECK: exit:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %loop.header
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@ -191,7 +166,7 @@ exit:
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ret void
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}
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define void @multiple_incoming_phi_with_blend_mask(i64 %a) {
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define void @multiple_incoming_phi_with_blend_mask(i64 %a, i16* noalias %dst) {
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; CHECK-LABEL: @multiple_incoming_phi_with_blend_mask(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
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@ -215,6 +190,12 @@ define void @multiple_incoming_phi_with_blend_mask(i64 %a) {
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; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds [32 x i16], [32 x i16]* @src, i16 0, i16 [[TMP6]]
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; CHECK-NEXT: [[TMP8:%.*]] = load i16, i16* [[TMP5]], align 1
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; CHECK-NEXT: [[TMP9:%.*]] = load i16, i16* [[TMP7]], align 1
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; CHECK-NEXT: [[INS1:%.+]] = insertelement <2 x i16> poison, i16 [[TMP8]], i32 0
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; CHECK-NEXT: [[INS2:%.+]] = insertelement <2 x i16> [[INS1]], i16 [[TMP9]], i32 1
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; CHECK-NEXT: [[DST0:%.+]] = getelementptr inbounds i16, i16* %dst, i64 [[TMP0]]
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; CHECK-NEXT: [[DST1:%.+]] = getelementptr inbounds i16, i16* [[DST0]], i32 0
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; CHECK-NEXT: [[DST1_BC:%.+]] = bitcast i16* [[DST1]] to <2 x i16>*
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; CHECK-NEXT: store <2 x i16> [[INS2]], <2 x i16>* [[DST1_BC]], align 2
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; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
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; CHECK-NEXT: [[VEC_IND_NEXT]] = add <2 x i64> [[VEC_IND]], <i64 2, i64 2>
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; CHECK-NEXT: [[VEC_IND_NEXT2]] = add <2 x i16> [[VEC_IND1]], <i16 2, i16 2>
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@ -224,26 +205,6 @@ define void @multiple_incoming_phi_with_blend_mask(i64 %a) {
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; CHECK: middle.block:
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; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 32, 32
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; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]]
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; CHECK: scalar.ph:
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; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 32, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ]
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; CHECK-NEXT: br label [[LOOP_HEADER:%.*]]
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; CHECK: loop.header:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP_LATCH:%.*]] ]
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; CHECK-NEXT: [[IV_TRUNC:%.*]] = trunc i64 [[IV]] to i16
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; CHECK-NEXT: [[IV_TRUNC_2:%.*]] = trunc i64 [[IV]] to i16
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; CHECK-NEXT: [[CMP_A:%.*]] = icmp ugt i64 [[IV]], [[A]]
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; CHECK-NEXT: br i1 [[CMP_A]], label [[LOOP_NEXT:%.*]], label [[LOOP_LATCH]]
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; CHECK: loop.next:
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; CHECK-NEXT: br label [[LOOP_LATCH]]
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; CHECK: loop.latch:
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; CHECK-NEXT: [[BLEND:%.*]] = phi i16 [ [[IV_TRUNC]], [[LOOP_HEADER]] ], [ [[IV_TRUNC_2]], [[LOOP_NEXT]] ]
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; CHECK-NEXT: [[SRC_PTR:%.*]] = getelementptr inbounds [32 x i16], [32 x i16]* @src, i16 0, i16 [[BLEND]]
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; CHECK-NEXT: [[LV:%.*]] = load i16, i16* [[SRC_PTR]], align 1
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; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
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; CHECK-NEXT: [[CMP439:%.*]] = icmp ult i64 [[IV]], 31
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; CHECK-NEXT: br i1 [[CMP439]], label [[LOOP_HEADER]], label [[EXIT]], [[LOOP7:!llvm.loop !.*]]
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; CHECK: exit:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %loop.header
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@ -262,6 +223,8 @@ loop.latch:
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%blend = phi i16 [ %iv.trunc, %loop.header ], [ %iv.trunc.2, %loop.next ]
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%src.ptr = getelementptr inbounds [32 x i16], [32 x i16]* @src, i16 0, i16 %blend
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%lv = load i16, i16* %src.ptr, align 1
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%dst.ptr = getelementptr inbounds i16, i16* %dst, i64 %iv
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store i16 %lv, i16* %dst.ptr
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%iv.next = add nuw nsw i64 %iv, 1
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%cmp439 = icmp ult i64 %iv, 31
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br i1 %cmp439, label %loop.header, label %exit
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@ -326,31 +289,6 @@ define void @single_incoming_needs_predication(i64 %a, i64 %b) {
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; CHECK: middle.block:
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; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 64, 64
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; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]]
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; CHECK: scalar.ph:
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; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 64, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ]
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; CHECK-NEXT: br label [[LOOP_HEADER:%.*]]
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; CHECK: loop.header:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP_LATCH:%.*]] ]
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; CHECK-NEXT: [[IV_TRUNC:%.*]] = trunc i64 [[IV]] to i16
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; CHECK-NEXT: [[CMP_A:%.*]] = icmp ugt i64 [[IV]], [[A]]
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; CHECK-NEXT: br i1 [[CMP_A]], label [[LOOP_COND:%.*]], label [[LOOP_LATCH]]
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; CHECK: loop.cond:
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; CHECK-NEXT: [[BLEND:%.*]] = phi i16 [ [[IV_TRUNC]], [[LOOP_HEADER]] ]
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; CHECK-NEXT: [[SRC_PTR:%.*]] = getelementptr inbounds [32 x i16], [32 x i16]* @src, i16 0, i16 [[BLEND]]
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; CHECK-NEXT: [[LV:%.*]] = load i16, i16* [[SRC_PTR]], align 1
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; CHECK-NEXT: [[CMP_B:%.*]] = icmp sgt i64 [[IV]], [[A]]
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; CHECK-NEXT: br i1 [[CMP_B]], label [[LOOP_NEXT:%.*]], label [[LOOP_LATCH]]
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; CHECK: loop.next:
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; CHECK-NEXT: br label [[LOOP_LATCH]]
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; CHECK: loop.latch:
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; CHECK-NEXT: [[RES:%.*]] = phi i16 [ 0, [[LOOP_HEADER]] ], [ [[LV]], [[LOOP_COND]] ], [ 1, [[LOOP_NEXT]] ]
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; CHECK-NEXT: [[DST_PTR:%.*]] = getelementptr inbounds [32 x i16], [32 x i16]* @dst, i16 0, i64 [[IV]]
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; CHECK-NEXT: store i16 [[RES]], i16* [[DST_PTR]], align 2
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; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
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; CHECK-NEXT: [[CMP439:%.*]] = icmp ult i64 [[IV]], 63
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; CHECK-NEXT: br i1 [[CMP439]], label [[LOOP_HEADER]], label [[EXIT]], [[LOOP9:!llvm.loop !.*]]
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; CHECK: exit:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %loop.header
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@ -408,22 +346,6 @@ define void @duplicated_incoming_blocks_blend(i32 %x, i32* %ptr) {
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; CHECK: middle.block:
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; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 1000, 1000
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; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]]
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; CHECK: scalar.ph:
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; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ 1000, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ]
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; CHECK-NEXT: br label [[LOOP_HEADER:%.*]]
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; CHECK: loop.header:
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[ADD_I:%.*]], [[LOOP_LATCH:%.*]] ]
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; CHECK-NEXT: [[C_0:%.*]] = icmp ugt i32 [[IV]], [[X]]
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; CHECK-NEXT: br i1 [[C_0]], label [[LOOP_LATCH]], label [[LOOP_LATCH]]
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; CHECK: loop.latch:
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; CHECK-NEXT: [[P:%.*]] = phi i32 [ [[IV]], [[LOOP_HEADER]] ], [ [[IV]], [[LOOP_HEADER]] ]
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; CHECK-NEXT: [[GEP_PTR:%.*]] = getelementptr i32, i32* [[PTR]], i32 [[P]]
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; CHECK-NEXT: store i32 [[P]], i32* [[GEP_PTR]], align 4
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; CHECK-NEXT: [[ADD_I]] = add nsw i32 [[P]], 1
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; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[ADD_I]], 1000
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; CHECK-NEXT: br i1 [[CMP]], label [[LOOP_HEADER]], label [[EXIT]], [[LOOP11:!llvm.loop !.*]]
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; CHECK: exit:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %loop.header
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@ -9,21 +9,49 @@
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; CHECK-REMARKS-NEXT: remark: {{.*}} interleaved loop (interleaved count: 4)
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; CHECK-REMARKS-NOT: remark: {{.*}} vectorized loop
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define void @VF1-VPlanExe() {
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define void @VF1-VPlanExe(i32* %dst) {
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; CHECK-LABEL: @VF1-VPlanExe(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
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; CHECK: vector.ph:
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; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
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; CHECK: vector.body:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
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; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE9:%.*]] ]
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; CHECK-NEXT: [[INDUCTION:%.*]] = add i64 [[INDEX]], 0
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; CHECK-NEXT: [[INDUCTION1:%.*]] = add i64 [[INDEX]], 1
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; CHECK-NEXT: [[INDUCTION2:%.*]] = add i64 [[INDEX]], 2
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; CHECK-NEXT: [[INDUCTION3:%.*]] = add i64 [[INDEX]], 3
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; CHECK-NEXT: [[TMP0:%.*]] = icmp ule i64 [[INDUCTION]], 14
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; CHECK-NEXT: [[TMP1:%.*]] = icmp ule i64 [[INDUCTION1]], 14
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; CHECK-NEXT: [[TMP2:%.*]] = icmp ule i64 [[INDUCTION2]], 14
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; CHECK-NEXT: [[TMP3:%.*]] = icmp ule i64 [[INDUCTION3]], 14
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; CHECK-NEXT: br i1 [[TMP0]], label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE:%.*]]
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; CHECK: pred.store.if:
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; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, i32* [[DST:%.*]], i64 [[INDUCTION]]
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; CHECK-NEXT: store i32 0, i32* [[TMP4]], align 4
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; CHECK-NEXT: br label [[PRED_STORE_CONTINUE]]
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; CHECK: pred.store.continue:
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; CHECK-NEXT: br i1 [[TMP1]], label [[PRED_STORE_IF4:%.*]], label [[PRED_STORE_CONTINUE5:%.*]]
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; CHECK: pred.store.if4:
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; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, i32* [[DST]], i64 [[INDUCTION1]]
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; CHECK-NEXT: store i32 0, i32* [[TMP5]], align 4
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; CHECK-NEXT: br label [[PRED_STORE_CONTINUE5]]
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; CHECK: pred.store.continue5:
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; CHECK-NEXT: br i1 [[TMP2]], label [[PRED_STORE_IF6:%.*]], label [[PRED_STORE_CONTINUE7:%.*]]
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; CHECK: pred.store.if6:
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; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, i32* [[DST]], i64 [[INDUCTION2]]
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; CHECK-NEXT: store i32 0, i32* [[TMP6]], align 4
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; CHECK-NEXT: br label [[PRED_STORE_CONTINUE7]]
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; CHECK: pred.store.continue7:
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; CHECK-NEXT: br i1 [[TMP3]], label [[PRED_STORE_IF8:%.*]], label [[PRED_STORE_CONTINUE9]]
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; CHECK: pred.store.if8:
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; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, i32* [[DST]], i64 [[INDUCTION3]]
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; CHECK-NEXT: store i32 0, i32* [[TMP7]], align 4
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; CHECK-NEXT: br label [[PRED_STORE_CONTINUE9]]
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; CHECK: pred.store.continue9:
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; CHECK-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 4
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; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i64 [[INDEX_NEXT]], 16
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; CHECK-NEXT: br i1 [[TMP0]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop !0
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; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], 16
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; CHECK-NEXT: br i1 [[TMP8]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
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; CHECK: middle.block:
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; CHECK-NEXT: br i1 true, label [[FOR_COND_CLEANUP:%.*]], label [[SCALAR_PH]]
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; CHECK: scalar.ph:
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@ -33,9 +61,11 @@ define void @VF1-VPlanExe() {
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; CHECK-NEXT: ret void
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; CHECK: for.body:
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; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ]
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; CHECK-NEXT: [[DST_PTR:%.*]] = getelementptr inbounds i32, i32* [[DST]], i64 [[INDVARS_IV]]
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; CHECK-NEXT: store i32 0, i32* [[DST_PTR]], align 4
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; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
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; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], 15
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; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY]], !llvm.loop !2
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; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY]], !llvm.loop [[LOOP2:![0-9]+]]
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;
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entry:
|
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br label %for.body
|
||||
|
|
@ -45,6 +75,8 @@ for.cond.cleanup:
|
|||
|
||||
for.body:
|
||||
%indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
|
||||
%dst.ptr = getelementptr inbounds i32, i32* %dst, i64 %indvars.iv
|
||||
store i32 0, i32* %dst.ptr
|
||||
%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
|
||||
%exitcond = icmp eq i64 %indvars.iv.next, 15
|
||||
br i1 %exitcond, label %for.cond.cleanup, label %for.body
|
||||
|
|
@ -59,18 +91,46 @@ define void @VF1-VPWidenCanonicalIVRecipeExe(double* %ptr1) {
|
|||
; CHECK-NEXT: [[IND_END:%.*]] = getelementptr double, double* [[PTR1]], i64 16
|
||||
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
|
||||
; CHECK: vector.body:
|
||||
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
|
||||
; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0
|
||||
; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr double, double* [[PTR1]], i64 [[TMP0]]
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 1
|
||||
; CHECK-NEXT: [[NEXT_GEP1:%.*]] = getelementptr double, double* [[PTR1]], i64 [[TMP1]]
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[INDEX]], 2
|
||||
; CHECK-NEXT: [[NEXT_GEP2:%.*]] = getelementptr double, double* [[PTR1]], i64 [[TMP2]]
|
||||
; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 3
|
||||
; CHECK-NEXT: [[NEXT_GEP3:%.*]] = getelementptr double, double* [[PTR1]], i64 [[TMP3]]
|
||||
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE12:%.*]] ]
|
||||
; CHECK-NEXT: [[VEC_IV:%.*]] = add i64 [[INDEX]], 0
|
||||
; CHECK-NEXT: [[VEC_IV4:%.*]] = add i64 [[INDEX]], 1
|
||||
; CHECK-NEXT: [[VEC_IV5:%.*]] = add i64 [[INDEX]], 2
|
||||
; CHECK-NEXT: [[VEC_IV6:%.*]] = add i64 [[INDEX]], 3
|
||||
; CHECK-NEXT: [[TMP0:%.*]] = icmp ule i64 [[VEC_IV]], 14
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = icmp ule i64 [[VEC_IV4]], 14
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = icmp ule i64 [[VEC_IV5]], 14
|
||||
; CHECK-NEXT: [[TMP3:%.*]] = icmp ule i64 [[VEC_IV6]], 14
|
||||
; CHECK-NEXT: br i1 [[TMP0]], label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE:%.*]]
|
||||
; CHECK: pred.store.if:
|
||||
; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[INDEX]], 0
|
||||
; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr double, double* [[PTR1]], i64 [[TMP4]]
|
||||
; CHECK-NEXT: store double 0.000000e+00, double* [[NEXT_GEP]], align 8
|
||||
; CHECK-NEXT: br label [[PRED_STORE_CONTINUE]]
|
||||
; CHECK: pred.store.continue:
|
||||
; CHECK-NEXT: br i1 [[TMP1]], label [[PRED_STORE_IF7:%.*]], label [[PRED_STORE_CONTINUE8:%.*]]
|
||||
; CHECK: pred.store.if7:
|
||||
; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[INDEX]], 1
|
||||
; CHECK-NEXT: [[NEXT_GEP1:%.*]] = getelementptr double, double* [[PTR1]], i64 [[TMP5]]
|
||||
; CHECK-NEXT: store double 0.000000e+00, double* [[NEXT_GEP1]], align 8
|
||||
; CHECK-NEXT: br label [[PRED_STORE_CONTINUE8]]
|
||||
; CHECK: pred.store.continue8:
|
||||
; CHECK-NEXT: br i1 [[TMP2]], label [[PRED_STORE_IF9:%.*]], label [[PRED_STORE_CONTINUE10:%.*]]
|
||||
; CHECK: pred.store.if9:
|
||||
; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[INDEX]], 2
|
||||
; CHECK-NEXT: [[NEXT_GEP2:%.*]] = getelementptr double, double* [[PTR1]], i64 [[TMP6]]
|
||||
; CHECK-NEXT: store double 0.000000e+00, double* [[NEXT_GEP2]], align 8
|
||||
; CHECK-NEXT: br label [[PRED_STORE_CONTINUE10]]
|
||||
; CHECK: pred.store.continue10:
|
||||
; CHECK-NEXT: br i1 [[TMP3]], label [[PRED_STORE_IF11:%.*]], label [[PRED_STORE_CONTINUE12]]
|
||||
; CHECK: pred.store.if11:
|
||||
; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[INDEX]], 3
|
||||
; CHECK-NEXT: [[NEXT_GEP3:%.*]] = getelementptr double, double* [[PTR1]], i64 [[TMP7]]
|
||||
; CHECK-NEXT: store double 0.000000e+00, double* [[NEXT_GEP3]], align 8
|
||||
; CHECK-NEXT: br label [[PRED_STORE_CONTINUE12]]
|
||||
; CHECK: pred.store.continue12:
|
||||
; CHECK-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 4
|
||||
; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[INDEX_NEXT]], 16
|
||||
; CHECK-NEXT: br i1 [[TMP4]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop !3
|
||||
; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], 16
|
||||
; CHECK-NEXT: br i1 [[TMP8]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
|
||||
; CHECK: middle.block:
|
||||
; CHECK-NEXT: br i1 true, label [[FOR_COND_CLEANUP:%.*]], label [[SCALAR_PH]]
|
||||
; CHECK: scalar.ph:
|
||||
|
|
@ -80,9 +140,10 @@ define void @VF1-VPWidenCanonicalIVRecipeExe(double* %ptr1) {
|
|||
; CHECK-NEXT: ret void
|
||||
; CHECK: for.body:
|
||||
; CHECK-NEXT: [[ADDR:%.*]] = phi double* [ [[PTR:%.*]], [[FOR_BODY]] ], [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ]
|
||||
; CHECK-NEXT: store double 0.000000e+00, double* [[ADDR]], align 8
|
||||
; CHECK-NEXT: [[PTR]] = getelementptr inbounds double, double* [[ADDR]], i64 1
|
||||
; CHECK-NEXT: [[COND:%.*]] = icmp eq double* [[PTR]], [[PTR2]]
|
||||
; CHECK-NEXT: br i1 [[COND]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY]], !llvm.loop !4
|
||||
; CHECK-NEXT: br i1 [[COND]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
|
||||
;
|
||||
entry:
|
||||
%ptr2 = getelementptr inbounds double, double* %ptr1, i64 15
|
||||
|
|
@ -93,6 +154,7 @@ for.cond.cleanup:
|
|||
|
||||
for.body:
|
||||
%addr = phi double* [ %ptr, %for.body ], [ %ptr1, %entry ]
|
||||
store double 0.0, double* %addr
|
||||
%ptr = getelementptr inbounds double, double* %addr, i64 1
|
||||
%cond = icmp eq double* %ptr, %ptr2
|
||||
br i1 %cond, label %for.cond.cleanup, label %for.body
|
||||
|
|
|
|||
|
|
@ -2,14 +2,18 @@
|
|||
|
||||
; CHECK-LABEL: @test_fshl
|
||||
; CHECK-LABEL: vector.body:
|
||||
; CHECK-NEXT: %index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ]
|
||||
; CHECK-NEXT: %0 = add i32 %index, 0
|
||||
; CHECK-NEXT: %1 = call <4 x i16> @llvm.fshl.v4i16(<4 x i16> undef, <4 x i16> undef, <4 x i16> <i16 15, i16 15, i16 15, i16 15>)
|
||||
; CHECK-NEXT: %index.next = add nuw i32 %index, 4
|
||||
; CHECK-NEXT: %2 = icmp eq i32 %index.next, %n.vec
|
||||
; CHECK-NEXT: br i1 %2, label %middle.block, label %vector.body, !llvm.loop !0
|
||||
; CHECK-NEXT: [[IDX:%.+]] = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ]
|
||||
; CHECK-NEXT: [[IDX0:%.+]] = add i32 %index, 0
|
||||
; CHECK-NEXT: [[FSHL:%.+]] = call <4 x i16> @llvm.fshl.v4i16(<4 x i16> undef, <4 x i16> undef, <4 x i16> <i16 15, i16 15, i16 15, i16 15>)
|
||||
; CHECK-NEXT: [[GEP0:%.+]] = getelementptr inbounds i16, i16* %dst, i32 [[IDX0]]
|
||||
; CHECK-NEXT: [[GEP1:%.+]] = getelementptr inbounds i16, i16* [[GEP0]], i32 0
|
||||
; CHECK-NEXT: [[GEP_BC:%.+]] = bitcast i16* [[GEP1]] to <4 x i16>*
|
||||
; CHECK-NEXT: store <4 x i16> [[FSHL]], <4 x i16>* [[GEP_BC]], align 2
|
||||
; CHECK-NEXT: [[IDX_NEXT:%.+]] = add nuw i32 [[IDX]], 4
|
||||
; CHECK-NEXT: [[EC:%.+]] = icmp eq i32 [[IDX_NEXT]], %n.vec
|
||||
; CHECK-NEXT: br i1 [[EC]], label %middle.block, label %vector.body
|
||||
;
|
||||
define void @test_fshl(i32 %width) {
|
||||
define void @test_fshl(i32 %width, i16* %dst) {
|
||||
entry:
|
||||
br label %for.body9.us.us
|
||||
|
||||
|
|
@ -17,10 +21,12 @@ for.cond6.for.cond.cleanup8_crit_edge.us.us: ; preds = %for.body9.us.us
|
|||
ret void
|
||||
|
||||
for.body9.us.us: ; preds = %for.body9.us.us, %entry
|
||||
%x.020.us.us = phi i32 [ 0, %entry ], [ %inc.us.us, %for.body9.us.us ]
|
||||
%iv = phi i32 [ 0, %entry ], [ %iv.next, %for.body9.us.us ]
|
||||
%conv4.i.us.us = tail call i16 @llvm.fshl.i16(i16 undef, i16 undef, i16 15)
|
||||
%inc.us.us = add nuw i32 %x.020.us.us, 1
|
||||
%exitcond50 = icmp eq i32 %inc.us.us, %width
|
||||
%dst.gep = getelementptr inbounds i16, i16* %dst, i32 %iv
|
||||
store i16 %conv4.i.us.us, i16* %dst.gep
|
||||
%iv.next = add nuw i32 %iv, 1
|
||||
%exitcond50 = icmp eq i32 %iv.next, %width
|
||||
br i1 %exitcond50, label %for.cond6.for.cond.cleanup8_crit_edge.us.us, label %for.body9.us.us
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue