forked from OSchip/llvm-project
[x86] Merge the second set of vector combining tests into a common test
file. Some of these really don't make sense to test -- we're testing for the *lack* of combining two shuffles into one, presumably because the two would generate better shuffles in the end. But if you look at the generated code shown here, in many cases the generated code is, frankly, terrible. Or we combine any two generated shuffles back into a single instruction! I've left a FIXME to revisit these decisions. llvm-svn: 218859
This commit is contained in:
Chandler Carruth
parent
2110501822
commit
b2941e2693
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@ -1,317 +0,0 @@
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; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 | FileCheck %s
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; Check that DAGCombiner correctly folds the following pairs of shuffles
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; using the following rules:
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; 1. shuffle(shuffle(x, y), undef) -> x
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; 2. shuffle(shuffle(x, y), undef) -> y
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; 3. shuffle(shuffle(x, y), undef) -> shuffle(x, undef)
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; 4. shuffle(shuffle(x, y), undef) -> shuffle(undef, y)
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;
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; Rules 3. and 4. are used only if the resulting shuffle mask is legal.
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define <4 x i32> @test1(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 3, i32 1>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 3>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test1
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; Mask: [3,0,0,1]
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; CHECK: pshufd $67
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; CHECK-NEXT: ret
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define <4 x i32> @test2(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 3>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test2
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; Mask: [2,0,0,3]
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; CHECK: pshufd $-62
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; CHECK-NEXT: ret
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define <4 x i32> @test3(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 6, i32 2, i32 3>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 3>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test3
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; Mask: [2,0,0,3]
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; CHECK: pshufd $-62
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; CHECK-NEXT: ret
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define <4 x i32> @test4(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 7, i32 1>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 4, i32 4, i32 0, i32 3>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test4
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; Mask: [0,0,0,1]
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; CHECK: pshufd $64
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; CHECK-NEXT: ret
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define <4 x i32> @test5(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 5, i32 5, i32 2, i32 3>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 4, i32 3>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test5
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; Mask: [1,1]
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; CHECK: movhlps
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; CHECK-NEXT: ret
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define <4 x i32> @test6(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 6, i32 2, i32 4>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 4>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test6
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; Mask: [2,0,0,0]
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; CHECK: pshufd $2
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; CHECK-NEXT: ret
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define <4 x i32> @test7(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 2, i32 0, i32 2>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test7
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; Mask: [0,2,0,2]
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; CHECK: pshufd $-120
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; CHECK-NEXT: ret
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define <4 x i32> @test8(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 4, i32 3, i32 4>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test8
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; Mask: [1,0,3,0]
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; CHECK: pshufd $49
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; CHECK-NEXT: ret
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define <4 x i32> @test9(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 3, i32 2, i32 5>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 4, i32 2>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test9
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; Mask: [1,3,0,2]
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; CHECK: pshufd $-115
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; CHECK-NEXT: ret
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define <4 x i32> @test10(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 1, i32 5, i32 5>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 4>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test10
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; Mask: [1,0,1,0]
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; CHECK: pshufd $17
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; CHECK-NEXT: ret
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define <4 x i32> @test11(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 2, i32 5, i32 4>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 0>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test11
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; Mask: [1,0,2,1]
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; CHECK: pshufd $97
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; CHECK-NEXT: ret
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define <4 x i32> @test12(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 0, i32 2, i32 4>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 4, i32 0, i32 4>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test12
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; Mask: [0,0,0,0]
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; CHECK: pshufd $0
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; CHECK-NEXT: ret
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; The following pair of shuffles is folded into vector %A.
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define <4 x i32> @test13(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 4, i32 2, i32 6>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 4, i32 0, i32 2, i32 4>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test13
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; CHECK-NOT: pshufd
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; CHECK: ret
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; The following pair of shuffles is folded into vector %B.
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define <4 x i32> @test14(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 6, i32 2, i32 4>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 3, i32 4, i32 1, i32 4>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test14
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; CHECK-NOT: pshufd
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; CHECK: ret
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; Verify that we don't optimize the following cases. We expect more than one shuffle.
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define <4 x i32> @test15(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 3, i32 1>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test15
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; CHECK: shufps $114
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; CHECK-NEXT: pshufd $-58
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; CHECK-NEXT: ret
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define <4 x i32> @test16(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test16
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; CHECK: blendps $10
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; CHECK-NEXT: pshufd $-58
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; CHECK-NEXT: ret
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define <4 x i32> @test17(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 3, i32 1>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test17
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; CHECK: shufps $120
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; CHECK-NEXT: pshufd $-58
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; CHECK-NEXT: ret
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define <4 x i32> @test18(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 0, i32 3>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test18
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; CHECK-NOT: blendps
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; CHECK: pshufd {{.*}} # xmm0 = xmm1[1,1,0,3]
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; CHECK-NEXT: ret
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define <4 x i32> @test19(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 5, i32 6>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 0, i32 0, i32 0>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test19
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; CHECK: shufps $-104
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; CHECK-NEXT: pshufd $2
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; CHECK-NEXT: ret
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define <4 x i32> @test20(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 3, i32 2, i32 4, i32 4>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test20
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; CHECK: shufps $11
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; CHECK-NEXT: pshufd $-58
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; CHECK-NEXT: ret
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define <4 x i32> @test21(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 3, i32 1>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 3>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test21
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; CHECK: shufps $120
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; CHECK-NEXT: pshufd $-60
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; CHECK-NEXT: ret
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; Test that we correctly combine shuffles according to rule
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; shuffle(shuffle(x, y), undef) -> shuffle(y, undef)
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define <4 x i32> @test22(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 3>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test22
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; CHECK-NOT: blendps
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; CHECK: pshufd {{.*}} # xmm0 = xmm1[1,1,1,3]
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; CHECK-NEXT: ret
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define <4 x i32> @test23(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 3>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test23
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; CHECK-NOT: blendps
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; CHECK: pshufd {{.*}} # xmm0 = xmm1[0,1,0,3]
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; CHECK-NEXT: ret
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define <4 x i32> @test24(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 6, i32 7>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 3, i32 2, i32 4>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test24
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; CHECK-NOT: blendps
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; CHECK: pshufd {{.*}} # xmm0 = xmm1[0,3,2,0]
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; CHECK-NEXT: ret
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define <4 x i32> @test25(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %B, <4 x i32> %A, <4 x i32> <i32 1, i32 5, i32 2, i32 4>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 3, i32 1, i32 3, i32 1>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test25
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; CHECK-NOT: shufps
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; CHECK: pshufd {{.*}} # xmm0 = xmm0[0,1,0,1]
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; CHECK-NEXT: ret
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define <4 x i32> @test26(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %B, <4 x i32> %A, <4 x i32> <i32 1, i32 2, i32 6, i32 7>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 2, i32 3>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test26
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; CHECK-NOT: shufps
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; CHECK: movhlps {{.*}} # xmm0 = xmm0[1,1]
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; CHECK-NEXT: ret
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define <4 x i32> @test27(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %B, <4 x i32> %A, <4 x i32> <i32 2, i32 1, i32 5, i32 4>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 3, i32 2>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test27
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; CHECK-NOT: shufps
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; CHECK-NOT: movhlps
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; CHECK: pshufd {{.*}} # xmm0 = xmm0[0,1,0,1]
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; CHECK-NEXT: ret
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define <4 x i32> @test28(<4 x i32> %A, <4 x i32> %B) {
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%1 = shufflevector <4 x i32> %B, <4 x i32> %A, <4 x i32> <i32 1, i32 2, i32 4, i32 5>
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 3, i32 2>
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ret <4 x i32> %2
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}
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; CHECK-LABEL: test28
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; CHECK-NOT: shufps
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; CHECK-NOT: movhlps
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; CHECK: pshufd {{.*}} # xmm0 = xmm0[0,1,1,0]
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; CHECK-NEXT: ret
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@ -627,3 +627,473 @@ define <4 x i32> @combine_bitwise_ops_test6c(<4 x i32> %a, <4 x i32> %b, <4 x i3
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%xor = xor <4 x i32> %shuf1, %shuf2
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ret <4 x i32> %xor
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}
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define <4 x i32> @combine_nested_undef_test1(<4 x i32> %A, <4 x i32> %B) {
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; SSE-LABEL: combine_nested_undef_test1:
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; SSE: # BB#0:
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; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,0,0,1]
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_nested_undef_test1:
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||||
; AVX: # BB#0:
|
||||
; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[3,0,0,1]
|
||||
; AVX-NEXT: retq
|
||||
%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 3, i32 1>
|
||||
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 3>
|
||||
ret <4 x i32> %2
|
||||
}
|
||||
|
||||
define <4 x i32> @combine_nested_undef_test2(<4 x i32> %A, <4 x i32> %B) {
|
||||
; SSE-LABEL: combine_nested_undef_test2:
|
||||
; SSE: # BB#0:
|
||||
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,0,0,3]
|
||||
; SSE-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: combine_nested_undef_test2:
|
||||
; AVX: # BB#0:
|
||||
; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,0,0,3]
|
||||
; AVX-NEXT: retq
|
||||
%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
|
||||
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 3>
|
||||
ret <4 x i32> %2
|
||||
}
|
||||
|
||||
define <4 x i32> @combine_nested_undef_test3(<4 x i32> %A, <4 x i32> %B) {
|
||||
; SSE-LABEL: combine_nested_undef_test3:
|
||||
; SSE: # BB#0:
|
||||
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,0,0,3]
|
||||
; SSE-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: combine_nested_undef_test3:
|
||||
; AVX: # BB#0:
|
||||
; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,0,0,3]
|
||||
; AVX-NEXT: retq
|
||||
%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 6, i32 2, i32 3>
|
||||
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 3>
|
||||
ret <4 x i32> %2
|
||||
}
|
||||
|
||||
define <4 x i32> @combine_nested_undef_test4(<4 x i32> %A, <4 x i32> %B) {
|
||||
; SSE-LABEL: combine_nested_undef_test4:
|
||||
; SSE: # BB#0:
|
||||
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,0,1]
|
||||
; SSE-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: combine_nested_undef_test4:
|
||||
; AVX: # BB#0:
|
||||
; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,1]
|
||||
; AVX-NEXT: retq
|
||||
%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 7, i32 1>
|
||||
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 4, i32 4, i32 0, i32 3>
|
||||
ret <4 x i32> %2
|
||||
}
|
||||
|
||||
define <4 x i32> @combine_nested_undef_test5(<4 x i32> %A, <4 x i32> %B) {
|
||||
; SSE-LABEL: combine_nested_undef_test5:
|
||||
; SSE: # BB#0:
|
||||
; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
|
||||
; SSE-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: combine_nested_undef_test5:
|
||||
; AVX: # BB#0:
|
||||
; AVX-NEXT: vmovhlps {{.*#+}} xmm0 = xmm0[1,1]
|
||||
; AVX-NEXT: retq
|
||||
%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 5, i32 5, i32 2, i32 3>
|
||||
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 4, i32 3>
|
||||
ret <4 x i32> %2
|
||||
}
|
||||
|
||||
define <4 x i32> @combine_nested_undef_test6(<4 x i32> %A, <4 x i32> %B) {
|
||||
; SSE-LABEL: combine_nested_undef_test6:
|
||||
; SSE: # BB#0:
|
||||
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,0,0,0]
|
||||
; SSE-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: combine_nested_undef_test6:
|
||||
; AVX: # BB#0:
|
||||
; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,0,0,0]
|
||||
; AVX-NEXT: retq
|
||||
%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 6, i32 2, i32 4>
|
||||
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 4, i32 0, i32 4>
|
||||
ret <4 x i32> %2
|
||||
}
|
||||
|
||||
define <4 x i32> @combine_nested_undef_test7(<4 x i32> %A, <4 x i32> %B) {
|
||||
; SSE-LABEL: combine_nested_undef_test7:
|
||||
; SSE: # BB#0:
|
||||
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,0,2]
|
||||
; SSE-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: combine_nested_undef_test7:
|
||||
; AVX: # BB#0:
|
||||
; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,0,2]
|
||||
; AVX-NEXT: retq
|
||||
%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
|
||||
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 2, i32 0, i32 2>
|
||||
ret <4 x i32> %2
|
||||
}
|
||||
|
||||
define <4 x i32> @combine_nested_undef_test8(<4 x i32> %A, <4 x i32> %B) {
|
||||
; SSE-LABEL: combine_nested_undef_test8:
|
||||
; SSE: # BB#0:
|
||||
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,0,3,0]
|
||||
; SSE-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: combine_nested_undef_test8:
|
||||
; AVX: # BB#0:
|
||||
; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,0,3,0]
|
||||
; AVX-NEXT: retq
|
||||
%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
|
||||
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 4, i32 3, i32 4>
|
||||
ret <4 x i32> %2
|
||||
}
|
||||
|
||||
define <4 x i32> @combine_nested_undef_test9(<4 x i32> %A, <4 x i32> %B) {
|
||||
; SSE-LABEL: combine_nested_undef_test9:
|
||||
; SSE: # BB#0:
|
||||
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,3,0,2]
|
||||
; SSE-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: combine_nested_undef_test9:
|
||||
; AVX: # BB#0:
|
||||
; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,3,0,2]
|
||||
; AVX-NEXT: retq
|
||||
%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 3, i32 2, i32 5>
|
||||
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 4, i32 2>
|
||||
ret <4 x i32> %2
|
||||
}
|
||||
|
||||
define <4 x i32> @combine_nested_undef_test10(<4 x i32> %A, <4 x i32> %B) {
|
||||
; SSE-LABEL: combine_nested_undef_test10:
|
||||
; SSE: # BB#0:
|
||||
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,0,1,0]
|
||||
; SSE-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: combine_nested_undef_test10:
|
||||
; AVX: # BB#0:
|
||||
; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,0,1,0]
|
||||
; AVX-NEXT: retq
|
||||
%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 1, i32 5, i32 5>
|
||||
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 4>
|
||||
ret <4 x i32> %2
|
||||
}
|
||||
|
||||
define <4 x i32> @combine_nested_undef_test11(<4 x i32> %A, <4 x i32> %B) {
|
||||
; SSE-LABEL: combine_nested_undef_test11:
|
||||
; SSE: # BB#0:
|
||||
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,0,2,1]
|
||||
; SSE-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: combine_nested_undef_test11:
|
||||
; AVX: # BB#0:
|
||||
; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,0,2,1]
|
||||
; AVX-NEXT: retq
|
||||
%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 2, i32 5, i32 4>
|
||||
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 0>
|
||||
ret <4 x i32> %2
|
||||
}
|
||||
|
||||
define <4 x i32> @combine_nested_undef_test12(<4 x i32> %A, <4 x i32> %B) {
|
||||
; SSE-LABEL: combine_nested_undef_test12:
|
||||
; SSE: # BB#0:
|
||||
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
|
||||
; SSE-NEXT: retq
|
||||
;
|
||||
; AVX1-LABEL: combine_nested_undef_test12:
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
|
||||
; AVX1-NEXT: retq
|
||||
;
|
||||
; AVX2-LABEL: combine_nested_undef_test12:
|
||||
; AVX2: # BB#0:
|
||||
; AVX2-NEXT: vbroadcastss %xmm0, %xmm0
|
||||
; AVX2-NEXT: retq
|
||||
%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 0, i32 2, i32 4>
|
||||
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 4, i32 0, i32 4>
|
||||
ret <4 x i32> %2
|
||||
}
|
||||
|
||||
; The following pair of shuffles is folded into vector %A.
|
||||
define <4 x i32> @combine_nested_undef_test13(<4 x i32> %A, <4 x i32> %B) {
|
||||
; ALL-LABEL: combine_nested_undef_test13:
|
||||
; ALL: # BB#0:
|
||||
; ALL-NEXT: retq
|
||||
%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 4, i32 2, i32 6>
|
||||
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 4, i32 0, i32 2, i32 4>
|
||||
ret <4 x i32> %2
|
||||
}
|
||||
|
||||
; The following pair of shuffles is folded into vector %B.
|
||||
define <4 x i32> @combine_nested_undef_test14(<4 x i32> %A, <4 x i32> %B) {
|
||||
; SSE-LABEL: combine_nested_undef_test14:
|
||||
; SSE: # BB#0:
|
||||
; SSE-NEXT: movaps %xmm1, %xmm0
|
||||
; SSE-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: combine_nested_undef_test14:
|
||||
; AVX: # BB#0:
|
||||
; AVX-NEXT: vmovaps %xmm1, %xmm0
|
||||
; AVX-NEXT: retq
|
||||
%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 6, i32 2, i32 4>
|
||||
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 3, i32 4, i32 1, i32 4>
|
||||
ret <4 x i32> %2
|
||||
}
|
||||
|
||||
|
||||
; Verify that we don't optimize the following cases. We expect more than one shuffle.
|
||||
;
|
||||
; FIXME: Many of these already don't make sense, and the rest should stop
|
||||
; making sense with th enew vector shuffle lowering. Revisit at least testing for
|
||||
; it.
|
||||
|
||||
define <4 x i32> @combine_nested_undef_test15(<4 x i32> %A, <4 x i32> %B) {
|
||||
; SSE-LABEL: combine_nested_undef_test15:
|
||||
; SSE: # BB#0:
|
||||
; SSE-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
|
||||
; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,1]
|
||||
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,1,0,3]
|
||||
; SSE-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: combine_nested_undef_test15:
|
||||
; AVX: # BB#0:
|
||||
; AVX-NEXT: vmovlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
|
||||
; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[2,0],xmm0[3,1]
|
||||
; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
|
||||
; AVX-NEXT: retq
|
||||
%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 3, i32 1>
|
||||
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
|
||||
ret <4 x i32> %2
|
||||
}
|
||||
|
||||
define <4 x i32> @combine_nested_undef_test16(<4 x i32> %A, <4 x i32> %B) {
|
||||
; SSE2-LABEL: combine_nested_undef_test16:
|
||||
; SSE2: # BB#0:
|
||||
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
|
||||
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,2,0,3]
|
||||
; SSE2-NEXT: retq
|
||||
;
|
||||
; SSSE3-LABEL: combine_nested_undef_test16:
|
||||
; SSSE3: # BB#0:
|
||||
; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
|
||||
; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,2,0,3]
|
||||
; SSSE3-NEXT: retq
|
||||
;
|
||||
; SSE41-LABEL: combine_nested_undef_test16:
|
||||
; SSE41: # BB#0:
|
||||
; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
|
||||
; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
|
||||
; SSE41-NEXT: retq
|
||||
;
|
||||
; AVX1-LABEL: combine_nested_undef_test16:
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
|
||||
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
|
||||
; AVX1-NEXT: retq
|
||||
;
|
||||
; AVX2-LABEL: combine_nested_undef_test16:
|
||||
; AVX2: # BB#0:
|
||||
; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
|
||||
; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
|
||||
; AVX2-NEXT: retq
|
||||
%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
|
||||
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
|
||||
ret <4 x i32> %2
|
||||
}
|
||||
|
||||
define <4 x i32> @combine_nested_undef_test17(<4 x i32> %A, <4 x i32> %B) {
|
||||
; SSE-LABEL: combine_nested_undef_test17:
|
||||
; SSE: # BB#0:
|
||||
; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[1,0]
|
||||
; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[3,1]
|
||||
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,1,0,3]
|
||||
; SSE-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: combine_nested_undef_test17:
|
||||
; AVX: # BB#0:
|
||||
; AVX-NEXT: vshufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[1,0]
|
||||
; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[0,2],xmm0[3,1]
|
||||
; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
|
||||
; AVX-NEXT: retq
|
||||
%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 3, i32 1>
|
||||
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
|
||||
ret <4 x i32> %2
|
||||
}
|
||||
|
||||
define <4 x i32> @combine_nested_undef_test18(<4 x i32> %A, <4 x i32> %B) {
|
||||
; SSE-LABEL: combine_nested_undef_test18:
|
||||
; SSE: # BB#0:
|
||||
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,0,3]
|
||||
; SSE-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: combine_nested_undef_test18:
|
||||
; AVX: # BB#0:
|
||||
; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm1[1,1,0,3]
|
||||
; AVX-NEXT: retq
|
||||
%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
|
||||
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 0, i32 3>
|
||||
ret <4 x i32> %2
|
||||
}
|
||||
|
||||
define <4 x i32> @combine_nested_undef_test19(<4 x i32> %A, <4 x i32> %B) {
|
||||
; SSE-LABEL: combine_nested_undef_test19:
|
||||
; SSE: # BB#0:
|
||||
; SSE-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
|
||||
; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,2]
|
||||
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,0,0,0]
|
||||
; SSE-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: combine_nested_undef_test19:
|
||||
; AVX: # BB#0:
|
||||
; AVX-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
|
||||
; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,2]
|
||||
; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,0,0,0]
|
||||
; AVX-NEXT: retq
|
||||
%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 5, i32 6>
|
||||
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 0, i32 0, i32 0>
|
||||
ret <4 x i32> %2
|
||||
}
|
||||
|
||||
define <4 x i32> @combine_nested_undef_test20(<4 x i32> %A, <4 x i32> %B) {
|
||||
; SSE-LABEL: combine_nested_undef_test20:
|
||||
; SSE: # BB#0:
|
||||
; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,2],xmm1[0,0]
|
||||
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
|
||||
; SSE-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: combine_nested_undef_test20:
|
||||
; AVX: # BB#0:
|
||||
; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[3,2],xmm1[0,0]
|
||||
; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
|
||||
; AVX-NEXT: retq
|
||||
%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 3, i32 2, i32 4, i32 4>
|
||||
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
|
||||
ret <4 x i32> %2
|
||||
}
|
||||
|
||||
define <4 x i32> @combine_nested_undef_test21(<4 x i32> %A, <4 x i32> %B) {
|
||||
; SSE-LABEL: combine_nested_undef_test21:
|
||||
; SSE: # BB#0:
|
||||
; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[1,0]
|
||||
; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[3,1]
|
||||
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,1,0,3]
|
||||
; SSE-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: combine_nested_undef_test21:
|
||||
; AVX: # BB#0:
|
||||
; AVX-NEXT: vshufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[1,0]
|
||||
; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[0,2],xmm0[3,1]
|
||||
; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,3]
|
||||
; AVX-NEXT: retq
|
||||
%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 3, i32 1>
|
||||
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 3>
|
||||
ret <4 x i32> %2
|
||||
}
|
||||
|
||||
|
||||
; Test that we correctly combine shuffles according to rule
|
||||
; shuffle(shuffle(x, y), undef) -> shuffle(y, undef)
|
||||
|
||||
define <4 x i32> @combine_nested_undef_test22(<4 x i32> %A, <4 x i32> %B) {
|
||||
; SSE-LABEL: combine_nested_undef_test22:
|
||||
; SSE: # BB#0:
|
||||
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,3]
|
||||
; SSE-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: combine_nested_undef_test22:
|
||||
; AVX: # BB#0:
|
||||
; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm1[1,1,1,3]
|
||||
; AVX-NEXT: retq
|
||||
%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
|
||||
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 3>
|
||||
ret <4 x i32> %2
|
||||
}
|
||||
|
||||
define <4 x i32> @combine_nested_undef_test23(<4 x i32> %A, <4 x i32> %B) {
|
||||
; SSE-LABEL: combine_nested_undef_test23:
|
||||
; SSE: # BB#0:
|
||||
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,1,0,3]
|
||||
; SSE-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: combine_nested_undef_test23:
|
||||
; AVX: # BB#0:
|
||||
; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm1[0,1,0,3]
|
||||
; AVX-NEXT: retq
|
||||
%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
|
||||
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 3>
|
||||
ret <4 x i32> %2
|
||||
}
|
||||
|
||||
define <4 x i32> @combine_nested_undef_test24(<4 x i32> %A, <4 x i32> %B) {
|
||||
; SSE-LABEL: combine_nested_undef_test24:
|
||||
; SSE: # BB#0:
|
||||
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,3,2,0]
|
||||
; SSE-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: combine_nested_undef_test24:
|
||||
; AVX: # BB#0:
|
||||
; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm1[0,3,2,0]
|
||||
; AVX-NEXT: retq
|
||||
%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 4, i32 1, i32 6, i32 7>
|
||||
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 3, i32 2, i32 4>
|
||||
ret <4 x i32> %2
|
||||
}
|
||||
|
||||
define <4 x i32> @combine_nested_undef_test25(<4 x i32> %A, <4 x i32> %B) {
|
||||
; SSE-LABEL: combine_nested_undef_test25:
|
||||
; SSE: # BB#0:
|
||||
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
|
||||
; SSE-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: combine_nested_undef_test25:
|
||||
; AVX: # BB#0:
|
||||
; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
|
||||
; AVX-NEXT: retq
|
||||
%1 = shufflevector <4 x i32> %B, <4 x i32> %A, <4 x i32> <i32 1, i32 5, i32 2, i32 4>
|
||||
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 3, i32 1, i32 3, i32 1>
|
||||
ret <4 x i32> %2
|
||||
}
|
||||
|
||||
define <4 x i32> @combine_nested_undef_test26(<4 x i32> %A, <4 x i32> %B) {
|
||||
; SSE-LABEL: combine_nested_undef_test26:
|
||||
; SSE: # BB#0:
|
||||
; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
|
||||
; SSE-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: combine_nested_undef_test26:
|
||||
; AVX: # BB#0:
|
||||
; AVX-NEXT: vmovhlps {{.*#+}} xmm0 = xmm0[1,1]
|
||||
; AVX-NEXT: retq
|
||||
%1 = shufflevector <4 x i32> %B, <4 x i32> %A, <4 x i32> <i32 1, i32 2, i32 6, i32 7>
|
||||
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 2, i32 3>
|
||||
ret <4 x i32> %2
|
||||
}
|
||||
|
||||
define <4 x i32> @combine_nested_undef_test27(<4 x i32> %A, <4 x i32> %B) {
|
||||
; SSE-LABEL: combine_nested_undef_test27:
|
||||
; SSE: # BB#0:
|
||||
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
|
||||
; SSE-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: combine_nested_undef_test27:
|
||||
; AVX: # BB#0:
|
||||
; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
|
||||
; AVX-NEXT: retq
|
||||
%1 = shufflevector <4 x i32> %B, <4 x i32> %A, <4 x i32> <i32 2, i32 1, i32 5, i32 4>
|
||||
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 3, i32 2>
|
||||
ret <4 x i32> %2
|
||||
}
|
||||
|
||||
define <4 x i32> @combine_nested_undef_test28(<4 x i32> %A, <4 x i32> %B) {
|
||||
; SSE-LABEL: combine_nested_undef_test28:
|
||||
; SSE: # BB#0:
|
||||
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,1,0]
|
||||
; SSE-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: combine_nested_undef_test28:
|
||||
; AVX: # BB#0:
|
||||
; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,1,0]
|
||||
; AVX-NEXT: retq
|
||||
%1 = shufflevector <4 x i32> %B, <4 x i32> %A, <4 x i32> <i32 1, i32 2, i32 4, i32 5>
|
||||
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 3, i32 2>
|
||||
ret <4 x i32> %2
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue