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[X86][XOP] Added support for VPMACSDQH/VPMACSDQL 'extension' IFMA patterns 

VPMACSDQH/VPMACSDQL act as VPADDQ( VPMULDQ( x, y ), z ) - multiply+extending either the odd/even 4i32 input elements and adding to v2i64 accumulator

llvm-svn: 292020
This commit is contained in:
Simon Pilgrim 2017-01-14 18:08:54 +00:00
parent a1631749f8
commit b290805e94
2 changed files with 18 additions and 17 deletions
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9
llvm/lib/Target/X86/X86InstrXOP.td
View File

@ -184,7 +184,7 @@ let ExeDomain = SSEPackedInt in {
}
// IFMA patterns - for cases where we can safely ignore the overflow bits from
// the multiply.
// the multiply or easily match with existing intrinsics.
let Predicates = [HasXOP] in {
def : Pat<(v8i16 (add (mul (v8i16 VR128:$src1), (v8i16 VR128:$src2)),
(v8i16 VR128:$src3))),
@ -192,6 +192,13 @@ let Predicates = [HasXOP] in {
def : Pat<(v4i32 (add (mul (v4i32 VR128:$src1), (v4i32 VR128:$src2)),
(v4i32 VR128:$src3))),
(VPMACSDDrr VR128:$src1, VR128:$src2, VR128:$src3)>;
def : Pat<(v2i64 (add (X86pmuldq (X86PShufd (v4i32 VR128:$src1), (i8 -11)),
(X86PShufd (v4i32 VR128:$src2), (i8 -11))),
(v2i64 VR128:$src3))),
(VPMACSDQHrr VR128:$src1, VR128:$src2, VR128:$src3)>;
def : Pat<(v2i64 (add (X86pmuldq (v4i32 VR128:$src1), (v4i32 VR128:$src2)),
(v2i64 VR128:$src3))),
(VPMACSDQLrr VR128:$src1, VR128:$src2, VR128:$src3)>;
}
// Instruction where second source can be memory, third must be imm8

26
llvm/test/CodeGen/X86/xop-ifma.ll
View File

@ -67,18 +67,16 @@ define <8 x i32> @test_mul_v8i32_add_v8i32(<8 x i32> %a0, <8 x i32> %a1, <8 x i3
define <4 x i64> @test_mulx_v4i32_add_v4i64(<4 x i32> %a0, <4 x i32> %a1, <4 x i64> %a2) {
; XOP-AVX1-LABEL: test_mulx_v4i32_add_v4i64:
; XOP-AVX1: # BB#0:
; XOP-AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm0[2,3,0,1]
; XOP-AVX1-NEXT: vpmovsxdq %xmm3, %xmm3
; XOP-AVX1-NEXT: vpmovsxdq %xmm0, %xmm3
; XOP-AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
; XOP-AVX1-NEXT: vpmovsxdq %xmm0, %xmm0
; XOP-AVX1-NEXT: vpshufd {{.*#+}} xmm4 = xmm1[2,3,0,1]
; XOP-AVX1-NEXT: vpmovsxdq %xmm4, %xmm4
; XOP-AVX1-NEXT: vpmovsxdq %xmm1, %xmm4
; XOP-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
; XOP-AVX1-NEXT: vpmovsxdq %xmm1, %xmm1
; XOP-AVX1-NEXT: vpmuldq %xmm1, %xmm0, %xmm0
; XOP-AVX1-NEXT: vpmuldq %xmm4, %xmm3, %xmm1
; XOP-AVX1-NEXT: vextractf128 $1, %ymm2, %xmm3
; XOP-AVX1-NEXT: vpaddq %xmm3, %xmm1, %xmm1
; XOP-AVX1-NEXT: vpaddq %xmm2, %xmm0, %xmm0
; XOP-AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; XOP-AVX1-NEXT: vextractf128 $1, %ymm2, %xmm5
; XOP-AVX1-NEXT: vpmacsdql %xmm5, %xmm1, %xmm0, %xmm0
; XOP-AVX1-NEXT: vpmacsdql %xmm2, %xmm4, %xmm3, %xmm1
; XOP-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; XOP-AVX1-NEXT: retq
;
; XOP-AVX2-LABEL: test_mulx_v4i32_add_v4i64:
@ -98,8 +96,7 @@ define <4 x i64> @test_mulx_v4i32_add_v4i64(<4 x i32> %a0, <4 x i32> %a1, <4 x i
define <2 x i64> @test_pmuldq_lo_v4i32_add_v2i64(<4 x i32> %a0, <4 x i32> %a1, <2 x i64> %a2) {
; XOP-LABEL: test_pmuldq_lo_v4i32_add_v2i64:
; XOP: # BB#0:
; XOP-NEXT: vpmuldq %xmm1, %xmm0, %xmm0
; XOP-NEXT: vpaddq %xmm2, %xmm0, %xmm0
; XOP-NEXT: vpmacsdql %xmm2, %xmm1, %xmm0, %xmm0
; XOP-NEXT: retq
%1 = call <2 x i64> @llvm.x86.sse41.pmuldq(<4 x i32> %a0, <4 x i32> %a1)
%2 = add <2 x i64> %1, %a2
@ -109,10 +106,7 @@ define <2 x i64> @test_pmuldq_lo_v4i32_add_v2i64(<4 x i32> %a0, <4 x i32> %a1, <
define <2 x i64> @test_pmuldq_hi_v4i32_add_v2i64(<4 x i32> %a0, <4 x i32> %a1, <2 x i64> %a2) {
; XOP-LABEL: test_pmuldq_hi_v4i32_add_v2i64:
; XOP: # BB#0:
; XOP-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
; XOP-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; XOP-NEXT: vpmuldq %xmm1, %xmm0, %xmm0
; XOP-NEXT: vpaddq %xmm2, %xmm0, %xmm0
; XOP-NEXT: vpmacsdqh %xmm2, %xmm1, %xmm0, %xmm0
; XOP-NEXT: retq
%1 = shufflevector <4 x i32> %a0, <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 3, i32 undef>
%2 = shufflevector <4 x i32> %a1, <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 3, i32 undef>