forked from OSchip/llvm-project
Transfer implicit operands in NEONMoveFixPass.
Later passes /are/ using this information when running the register scavenger. This fixes the second problem in PR10520. llvm-svn: 136440
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@ -40,6 +40,8 @@ namespace {
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typedef DenseMap<unsigned, const MachineInstr*> RegMap;
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bool InsertMoves(MachineBasicBlock &MBB);
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void TransferImpOps(MachineInstr &Old, MachineInstr &New);
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};
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char NEONMoveFixPass::ID = 0;
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}
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@ -49,6 +51,16 @@ static bool inNEONDomain(unsigned Domain, bool isA8) {
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(isA8 && (Domain & ARMII::DomainNEONA8));
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}
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/// Transfer implicit kill and def operands from Old to New.
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void NEONMoveFixPass::TransferImpOps(MachineInstr &Old, MachineInstr &New) {
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for (unsigned i = 0, e = Old.getNumOperands(); i != e; ++i) {
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MachineOperand &MO = Old.getOperand(i);
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if (!MO.isReg() || !MO.isImplicit())
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continue;
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New.addOperand(MO);
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}
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}
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bool NEONMoveFixPass::InsertMoves(MachineBasicBlock &MBB) {
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RegMap Defs;
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bool Modified = false;
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@ -82,17 +94,15 @@ bool NEONMoveFixPass::InsertMoves(MachineBasicBlock &MBB) {
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DEBUG({errs() << "vmov convert: "; MI->dump();});
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// It's safe to ignore imp-defs / imp-uses here, since:
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// - We're running late, no intelligent condegen passes should be run
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// afterwards
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// - The imp-defs / imp-uses are superregs only, we don't care about
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// them.
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AddDefaultPred(BuildMI(MBB, *MI, MI->getDebugLoc(),
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TII->get(ARM::VORRd), DestReg)
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.addReg(SrcReg).addReg(SrcReg));
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// We need to preserve imp-defs / imp-uses here. Following passes may
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// use the register scavenger to update liveness.
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MachineInstr *NewMI =
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AddDefaultPred(BuildMI(MBB, *MI, MI->getDebugLoc(),
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TII->get(ARM::VORRd), DestReg)
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.addReg(SrcReg).addReg(SrcReg));
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TransferImpOps(*MI, *NewMI);
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MBB.erase(MI);
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MachineBasicBlock::iterator I = prior(NextMII);
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MI = &*I;
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MI = NewMI;
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DEBUG({errs() << " into: "; MI->dump();});
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@ -48,3 +48,24 @@ bb:
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store <4 x float> %tmp20, <4 x float>* undef, align 16
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ret void
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}
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; PR10520, second bug. NEONMoveFixPass needs to preserve implicit operands.
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define arm_aapcs_vfpcc void @pr10520_2() nounwind align 2 {
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bb:
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%tmp76 = shufflevector <2 x i64> zeroinitializer, <2 x i64> zeroinitializer, <1 x i32> <i32 1>
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%tmp77 = bitcast <1 x i64> %tmp76 to <2 x float>
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%tmp78 = shufflevector <2 x float> %tmp77, <2 x float> %tmp77, <4 x i32> zeroinitializer
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%tmp81 = fmul <4 x float> undef, %tmp78
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%tmp82 = fadd <4 x float> %tmp81, undef
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%tmp85 = fadd <4 x float> %tmp82, undef
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%tmp86 = bitcast <4 x float> %tmp85 to i128
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%tmp136 = bitcast i128 %tmp86 to <4 x float>
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%tmp137 = bitcast <4 x float> %tmp136 to i128
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%tmp138 = bitcast i128 %tmp137 to <4 x float>
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%tmp139 = bitcast <4 x float> %tmp138 to i128
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%tmp152 = bitcast i128 %tmp139 to <4 x float>
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%tmp153 = bitcast <4 x float> %tmp152 to i128
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%tmp154 = bitcast i128 %tmp153 to <4 x float>
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store <4 x float> %tmp154, <4 x float>* undef, align 16
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ret void
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}
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