[mlir][spirv] Fix bitcast input order for UnifyAliasedResourcePass

spv.bitcast from a vector to a scalar expects the lower-numbered
components of the the vector to map to the lower-ordered bits of
the scalar. That actually already matches how little endian stores
data in the memory. So we just need to read and push to the back
of the vector sequentially.

Reviewed By: hanchung

Differential Revision: https://reviews.llvm.org/D128473
This commit is contained in:
Lei Zhang 2022-06-23 22:19:08 -04:00
parent 9aaba9d9bb
commit b2671d8898
2 changed files with 5 additions and 3 deletions

View File

@ -455,12 +455,14 @@ struct ConvertLoad : public ConvertAliasResource<spirv::LoadOp> {
indices.back(), oneValue);
auto componentAcOp =
rewriter.create<spirv::AccessChainOp>(loc, acOp.base_ptr(), indices);
// Assuming little endian, this reads lower-ordered bits of the number to
// lower-numbered components of the vector.
components.push_back(rewriter.create<spirv::LoadOp>(loc, componentAcOp));
}
std::reverse(components.begin(), components.end()); // For little endian..
// Create a vector of the components and then cast back to the larger
// bitwidth element type.
// bitwidth element type. For spv.bitcast, the lower-numbered components of
// the vector map to lower-ordered bits of the larger bitwidth element type.
auto vectorType = VectorType::get({ratio}, dstElemType);
Value vectorValue = rewriter.create<spirv::CompositeConstructOp>(
loc, vectorType, components);

View File

@ -251,7 +251,7 @@ spv.module Logical GLSL450 {
// CHECK: %[[AC1:.+]] = spv.AccessChain %[[ADDR]][%[[ZERO]], %[[ADD]]]
// CHECK: %[[LOAD1:.+]] = spv.Load "StorageBuffer" %[[AC1]] : f32
// CHECK: %[[CC:.+]] = spv.CompositeConstruct %[[LOAD1]], %[[LOAD0]]
// CHECK: %[[CC:.+]] = spv.CompositeConstruct %[[LOAD0]], %[[LOAD1]]
// CHECK: %[[CAST:.+]] = spv.Bitcast %[[CC]] : vector<2xf32> to i64
// CHECK: spv.ReturnValue %[[CAST]]