[SPIRV] use tablegen to create SPIRVBaseInfo*

The patch replaces SPIRVBaseInfo.* previously created using macros by
the tablegen approach. There are many small changes in other files due to
differences in namespaces. Also, functions in SPIRVUtils are moved to
the llvm namespace.

Differential Revision: https://reviews.llvm.org/D130518

Co-authored-by: Aleksandr Bezzubikov <zuban32s@gmail.com>
Co-authored-by: Michal Paszkowski <michal.paszkowski@outlook.com>
Co-authored-by: Andrey Tretyakov <andrey1.tretyakov@intel.com>
Co-authored-by: Konrad Trifunovic <konrad.trifunovic@intel.com>
This commit is contained in:
Ilia Diachkov 2022-08-01 22:56:31 +03:00
parent 6b3fa58fde
commit b25b507c77
17 changed files with 2032 additions and 2220 deletions

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@ -9,6 +9,7 @@ tablegen(LLVM SPIRVGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM SPIRVGenRegisterBank.inc -gen-register-bank)
tablegen(LLVM SPIRVGenRegisterInfo.inc -gen-register-info)
tablegen(LLVM SPIRVGenSubtargetInfo.inc -gen-subtarget)
tablegen(LLVM SPIRVGenTables.inc -gen-searchable-tables)
add_public_tablegen_target(SPIRVCommonTableGen)

File diff suppressed because it is too large Load Diff

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@ -1,4 +1,4 @@
//===-- SPIRVBaseInfo.h - Top level definitions for SPIRV ------*- C++ -*-===//
//===-- SPIRVBaseInfo.h - Top level SPIRV definitions -----------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
@ -6,706 +6,195 @@
//
//===----------------------------------------------------------------------===//
//
// This file contains small standalone helper functions and enum definitions for
// the SPIRV target useful for the compiler back-end and the MC libraries.
// As such, it deliberately does not include references to LLVM core
// code gen types, passes, etc..
// This file contains TableGen generated enum definitions, mnemonic lookup
// functions, versioning/capabilities/extensions getters for symbolic/named
// operands for various SPIR-V instructions.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_LIB_TARGET_SPIRV_MCTARGETDESC_SPIRVBASEINFO_H
#define LLVM_LIB_TARGET_SPIRV_MCTARGETDESC_SPIRVBASEINFO_H
#ifndef LLVM_LIB_TARGET_SPIRV_SPIRVSYMBOLICOPERANDS_H
#define LLVM_LIB_TARGET_SPIRV_SPIRVSYMBOLICOPERANDS_H
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringRef.h"
#include <string>
namespace llvm {
namespace SPIRV {
enum class Capability : uint32_t {
Matrix = 0,
Shader = 1,
Geometry = 2,
Tessellation = 3,
Addresses = 4,
Linkage = 5,
Kernel = 6,
Vector16 = 7,
Float16Buffer = 8,
Float16 = 9,
Float64 = 10,
Int64 = 11,
Int64Atomics = 12,
ImageBasic = 13,
ImageReadWrite = 14,
ImageMipmap = 15,
Pipes = 17,
Groups = 18,
DeviceEnqueue = 19,
LiteralSampler = 20,
AtomicStorage = 21,
Int16 = 22,
TessellationPointSize = 23,
GeometryPointSize = 24,
ImageGatherExtended = 25,
StorageImageMultisample = 27,
UniformBufferArrayDynamicIndexing = 28,
SampledImageArrayDymnamicIndexing = 29,
ClipDistance = 32,
CullDistance = 33,
ImageCubeArray = 34,
SampleRateShading = 35,
ImageRect = 36,
SampledRect = 37,
GenericPointer = 38,
Int8 = 39,
InputAttachment = 40,
SparseResidency = 41,
MinLod = 42,
Sampled1D = 43,
Image1D = 44,
SampledCubeArray = 45,
SampledBuffer = 46,
ImageBuffer = 47,
ImageMSArray = 48,
StorageImageExtendedFormats = 49,
ImageQuery = 50,
DerivativeControl = 51,
InterpolationFunction = 52,
TransformFeedback = 53,
GeometryStreams = 54,
StorageImageReadWithoutFormat = 55,
StorageImageWriteWithoutFormat = 56,
MultiViewport = 57,
SubgroupDispatch = 58,
NamedBarrier = 59,
PipeStorage = 60,
GroupNonUniform = 61,
GroupNonUniformVote = 62,
GroupNonUniformArithmetic = 63,
GroupNonUniformBallot = 64,
GroupNonUniformShuffle = 65,
GroupNonUniformShuffleRelative = 66,
GroupNonUniformClustered = 67,
GroupNonUniformQuad = 68,
SubgroupBallotKHR = 4423,
DrawParameters = 4427,
SubgroupVoteKHR = 4431,
StorageBuffer16BitAccess = 4433,
StorageUniform16 = 4434,
StoragePushConstant16 = 4435,
StorageInputOutput16 = 4436,
DeviceGroup = 4437,
MultiView = 4439,
VariablePointersStorageBuffer = 4441,
VariablePointers = 4442,
AtomicStorageOps = 4445,
SampleMaskPostDepthCoverage = 4447,
StorageBuffer8BitAccess = 4448,
UniformAndStorageBuffer8BitAccess = 4449,
StoragePushConstant8 = 4450,
DenormPreserve = 4464,
DenormFlushToZero = 4465,
SignedZeroInfNanPreserve = 4466,
RoundingModeRTE = 4467,
RoundingModeRTZ = 4468,
Float16ImageAMD = 5008,
ImageGatherBiasLodAMD = 5009,
FragmentMaskAMD = 5010,
StencilExportEXT = 5013,
ImageReadWriteLodAMD = 5015,
SampleMaskOverrideCoverageNV = 5249,
GeometryShaderPassthroughNV = 5251,
ShaderViewportIndexLayerEXT = 5254,
ShaderViewportMaskNV = 5255,
ShaderStereoViewNV = 5259,
PerViewAttributesNV = 5260,
FragmentFullyCoveredEXT = 5265,
MeshShadingNV = 5266,
ShaderNonUniformEXT = 5301,
RuntimeDescriptorArrayEXT = 5302,
InputAttachmentArrayDynamicIndexingEXT = 5303,
UniformTexelBufferArrayDynamicIndexingEXT = 5304,
StorageTexelBufferArrayDynamicIndexingEXT = 5305,
UniformBufferArrayNonUniformIndexingEXT = 5306,
SampledImageArrayNonUniformIndexingEXT = 5307,
StorageBufferArrayNonUniformIndexingEXT = 5308,
StorageImageArrayNonUniformIndexingEXT = 5309,
InputAttachmentArrayNonUniformIndexingEXT = 5310,
UniformTexelBufferArrayNonUniformIndexingEXT = 5311,
StorageTexelBufferArrayNonUniformIndexingEXT = 5312,
RayTracingNV = 5340,
SubgroupShuffleINTEL = 5568,
SubgroupBufferBlockIOINTEL = 5569,
SubgroupImageBlockIOINTEL = 5570,
SubgroupImageMediaBlockIOINTEL = 5579,
SubgroupAvcMotionEstimationINTEL = 5696,
SubgroupAvcMotionEstimationIntraINTEL = 5697,
SubgroupAvcMotionEstimationChromaINTEL = 5698,
GroupNonUniformPartitionedNV = 5297,
VulkanMemoryModelKHR = 5345,
VulkanMemoryModelDeviceScopeKHR = 5346,
ImageFootprintNV = 5282,
FragmentBarycentricNV = 5284,
ComputeDerivativeGroupQuadsNV = 5288,
ComputeDerivativeGroupLinearNV = 5350,
FragmentDensityEXT = 5291,
PhysicalStorageBufferAddressesEXT = 5347,
CooperativeMatrixNV = 5357,
};
StringRef getCapabilityName(Capability e);
namespace OperandCategory {
#define GET_OperandCategory_DECL
#include "SPIRVGenTables.inc"
} // namespace OperandCategory
enum class SourceLanguage : uint32_t {
Unknown = 0,
ESSL = 1,
GLSL = 2,
OpenCL_C = 3,
OpenCL_CPP = 4,
HLSL = 5,
};
StringRef getSourceLanguageName(SourceLanguage e);
namespace Extension {
#define GET_Extension_DECL
#include "SPIRVGenTables.inc"
} // namespace Extension
enum class AddressingModel : uint32_t {
Logical = 0,
Physical32 = 1,
Physical64 = 2,
PhysicalStorageBuffer64EXT = 5348,
};
StringRef getAddressingModelName(AddressingModel e);
namespace Capability {
#define GET_Capability_DECL
#include "SPIRVGenTables.inc"
} // namespace Capability
enum class ExecutionModel : uint32_t {
Vertex = 0,
TessellationControl = 1,
TessellationEvaluation = 2,
Geometry = 3,
Fragment = 4,
GLCompute = 5,
Kernel = 6,
TaskNV = 5267,
MeshNV = 5268,
RayGenerationNV = 5313,
IntersectionNV = 5314,
AnyHitNV = 5315,
ClosestHitNV = 5316,
MissNV = 5317,
CallableNV = 5318,
};
StringRef getExecutionModelName(ExecutionModel e);
namespace SourceLanguage {
#define GET_SourceLanguage_DECL
#include "SPIRVGenTables.inc"
} // namespace SourceLanguage
enum class MemoryModel : uint32_t {
Simple = 0,
GLSL450 = 1,
OpenCL = 2,
VulkanKHR = 3,
};
StringRef getMemoryModelName(MemoryModel e);
namespace AddressingModel {
#define GET_AddressingModel_DECL
#include "SPIRVGenTables.inc"
} // namespace AddressingModel
enum class ExecutionMode : uint32_t {
Invocations = 0,
SpacingEqual = 1,
SpacingFractionalEven = 2,
SpacingFractionalOdd = 3,
VertexOrderCw = 4,
VertexOrderCcw = 5,
PixelCenterInteger = 6,
OriginUpperLeft = 7,
OriginLowerLeft = 8,
EarlyFragmentTests = 9,
PointMode = 10,
Xfb = 11,
DepthReplacing = 12,
DepthGreater = 14,
DepthLess = 15,
DepthUnchanged = 16,
LocalSize = 17,
LocalSizeHint = 18,
InputPoints = 19,
InputLines = 20,
InputLinesAdjacency = 21,
Triangles = 22,
InputTrianglesAdjacency = 23,
Quads = 24,
Isolines = 25,
OutputVertices = 26,
OutputPoints = 27,
OutputLineStrip = 28,
OutputTriangleStrip = 29,
VecTypeHint = 30,
ContractionOff = 31,
Initializer = 33,
Finalizer = 34,
SubgroupSize = 35,
SubgroupsPerWorkgroup = 36,
SubgroupsPerWorkgroupId = 37,
LocalSizeId = 38,
LocalSizeHintId = 39,
PostDepthCoverage = 4446,
DenormPreserve = 4459,
DenormFlushToZero = 4460,
SignedZeroInfNanPreserve = 4461,
RoundingModeRTE = 4462,
RoundingModeRTZ = 4463,
StencilRefReplacingEXT = 5027,
OutputLinesNV = 5269,
DerivativeGroupQuadsNV = 5289,
DerivativeGroupLinearNV = 5290,
OutputTrianglesNV = 5298,
};
StringRef getExecutionModeName(ExecutionMode e);
namespace ExecutionModel {
#define GET_ExecutionModel_DECL
#include "SPIRVGenTables.inc"
} // namespace ExecutionModel
enum class StorageClass : uint32_t {
UniformConstant = 0,
Input = 1,
Uniform = 2,
Output = 3,
Workgroup = 4,
CrossWorkgroup = 5,
Private = 6,
Function = 7,
Generic = 8,
PushConstant = 9,
AtomicCounter = 10,
Image = 11,
StorageBuffer = 12,
CallableDataNV = 5328,
IncomingCallableDataNV = 5329,
RayPayloadNV = 5338,
HitAttributeNV = 5339,
IncomingRayPayloadNV = 5342,
ShaderRecordBufferNV = 5343,
PhysicalStorageBufferEXT = 5349,
};
StringRef getStorageClassName(StorageClass e);
namespace MemoryModel {
#define GET_MemoryModel_DECL
#include "SPIRVGenTables.inc"
} // namespace MemoryModel
enum class Dim : uint32_t {
DIM_1D = 0,
DIM_2D = 1,
DIM_3D = 2,
DIM_Cube = 3,
DIM_Rect = 4,
DIM_Buffer = 5,
DIM_SubpassData = 6,
};
StringRef getDimName(Dim e);
namespace ExecutionMode {
#define GET_ExecutionMode_DECL
#include "SPIRVGenTables.inc"
} // namespace ExecutionMode
enum class SamplerAddressingMode : uint32_t {
None = 0,
ClampToEdge = 1,
Clamp = 2,
Repeat = 3,
RepeatMirrored = 4,
};
StringRef getSamplerAddressingModeName(SamplerAddressingMode e);
namespace StorageClass {
#define GET_StorageClass_DECL
#include "SPIRVGenTables.inc"
} // namespace StorageClass
enum class SamplerFilterMode : uint32_t {
Nearest = 0,
Linear = 1,
};
StringRef getSamplerFilterModeName(SamplerFilterMode e);
namespace Dim {
#define GET_Dim_DECL
#include "SPIRVGenTables.inc"
} // namespace Dim
enum class ImageFormat : uint32_t {
Unknown = 0,
Rgba32f = 1,
Rgba16f = 2,
R32f = 3,
Rgba8 = 4,
Rgba8Snorm = 5,
Rg32f = 6,
Rg16f = 7,
R11fG11fB10f = 8,
R16f = 9,
Rgba16 = 10,
Rgb10A2 = 11,
Rg16 = 12,
Rg8 = 13,
R16 = 14,
R8 = 15,
Rgba16Snorm = 16,
Rg16Snorm = 17,
Rg8Snorm = 18,
R16Snorm = 19,
R8Snorm = 20,
Rgba32i = 21,
Rgba16i = 22,
Rgba8i = 23,
R32i = 24,
Rg32i = 25,
Rg16i = 26,
Rg8i = 27,
R16i = 28,
R8i = 29,
Rgba32ui = 30,
Rgba16ui = 31,
Rgba8ui = 32,
R32ui = 33,
Rgb10a2ui = 34,
Rg32ui = 35,
Rg16ui = 36,
Rg8ui = 37,
R16ui = 38,
R8ui = 39,
};
StringRef getImageFormatName(ImageFormat e);
namespace SamplerAddressingMode {
#define GET_SamplerAddressingMode_DECL
#include "SPIRVGenTables.inc"
} // namespace SamplerAddressingMode
enum class ImageChannelOrder : uint32_t {
R = 0,
A = 1,
RG = 2,
RA = 3,
RGB = 4,
RGBA = 5,
BGRA = 6,
ARGB = 7,
Intensity = 8,
Luminance = 9,
Rx = 10,
RGx = 11,
RGBx = 12,
Depth = 13,
DepthStencil = 14,
sRGB = 15,
sRGBx = 16,
sRGBA = 17,
sBGRA = 18,
ABGR = 19,
};
StringRef getImageChannelOrderName(ImageChannelOrder e);
namespace SamplerFilterMode {
#define GET_SamplerFilterMode_DECL
#include "SPIRVGenTables.inc"
} // namespace SamplerFilterMode
enum class ImageChannelDataType : uint32_t {
SnormInt8 = 0,
SnormInt16 = 1,
UnormInt8 = 2,
UnormInt16 = 3,
UnormShort565 = 4,
UnormShort555 = 5,
UnormInt101010 = 6,
SignedInt8 = 7,
SignedInt16 = 8,
SignedInt32 = 9,
UnsignedInt8 = 10,
UnsignedInt16 = 11,
UnsigendInt32 = 12,
HalfFloat = 13,
Float = 14,
UnormInt24 = 15,
UnormInt101010_2 = 16,
};
StringRef getImageChannelDataTypeName(ImageChannelDataType e);
namespace ImageFormat {
#define GET_ImageFormat_DECL
#include "SPIRVGenTables.inc"
} // namespace ImageFormat
enum class ImageOperand : uint32_t {
None = 0x0,
Bias = 0x1,
Lod = 0x2,
Grad = 0x4,
ConstOffset = 0x8,
Offset = 0x10,
ConstOffsets = 0x20,
Sample = 0x40,
MinLod = 0x80,
MakeTexelAvailableKHR = 0x100,
MakeTexelVisibleKHR = 0x200,
NonPrivateTexelKHR = 0x400,
VolatileTexelKHR = 0x800,
SignExtend = 0x1000,
ZeroExtend = 0x2000,
};
std::string getImageOperandName(uint32_t e);
namespace ImageChannelOrder {
#define GET_ImageChannelOrder_DECL
#include "SPIRVGenTables.inc"
} // namespace ImageChannelOrder
enum class FPFastMathMode : uint32_t {
None = 0x0,
NotNaN = 0x1,
NotInf = 0x2,
NSZ = 0x4,
AllowRecip = 0x8,
Fast = 0x10,
};
std::string getFPFastMathModeName(uint32_t e);
namespace ImageChannelDataType {
#define GET_ImageChannelDataType_DECL
#include "SPIRVGenTables.inc"
} // namespace ImageChannelDataType
enum class FPRoundingMode : uint32_t {
RTE = 0,
RTZ = 1,
RTP = 2,
RTN = 3,
};
StringRef getFPRoundingModeName(FPRoundingMode e);
namespace ImageOperand {
#define GET_ImageOperand_DECL
#include "SPIRVGenTables.inc"
} // namespace ImageOperand
enum class LinkageType : uint32_t {
Export = 0,
Import = 1,
};
StringRef getLinkageTypeName(LinkageType e);
namespace FPFastMathMode {
#define GET_FPFastMathMode_DECL
#include "SPIRVGenTables.inc"
} // namespace FPFastMathMode
enum class AccessQualifier : uint32_t {
ReadOnly = 0,
WriteOnly = 1,
ReadWrite = 2,
};
StringRef getAccessQualifierName(AccessQualifier e);
namespace FPRoundingMode {
#define GET_FPRoundingMode_DECL
#include "SPIRVGenTables.inc"
} // namespace FPRoundingMode
enum class FunctionParameterAttribute : uint32_t {
Zext = 0,
Sext = 1,
ByVal = 2,
Sret = 3,
NoAlias = 4,
NoCapture = 5,
NoWrite = 6,
NoReadWrite = 7,
};
StringRef getFunctionParameterAttributeName(FunctionParameterAttribute e);
namespace LinkageType {
#define GET_LinkageType_DECL
#include "SPIRVGenTables.inc"
} // namespace LinkageType
enum class Decoration : uint32_t {
RelaxedPrecision = 0,
SpecId = 1,
Block = 2,
BufferBlock = 3,
RowMajor = 4,
ColMajor = 5,
ArrayStride = 6,
MatrixStride = 7,
GLSLShared = 8,
GLSLPacked = 9,
CPacked = 10,
BuiltIn = 11,
NoPerspective = 13,
Flat = 14,
Patch = 15,
Centroid = 16,
Sample = 17,
Invariant = 18,
Restrict = 19,
Aliased = 20,
Volatile = 21,
Constant = 22,
Coherent = 23,
NonWritable = 24,
NonReadable = 25,
Uniform = 26,
UniformId = 27,
SaturatedConversion = 28,
Stream = 29,
Location = 30,
Component = 31,
Index = 32,
Binding = 33,
DescriptorSet = 34,
Offset = 35,
XfbBuffer = 36,
XfbStride = 37,
FuncParamAttr = 38,
FPRoundingMode = 39,
FPFastMathMode = 40,
LinkageAttributes = 41,
NoContraction = 42,
InputAttachmentIndex = 43,
Alignment = 44,
MaxByteOffset = 45,
AlignmentId = 46,
MaxByteOffsetId = 47,
NoSignedWrap = 4469,
NoUnsignedWrap = 4470,
ExplicitInterpAMD = 4999,
OverrideCoverageNV = 5248,
PassthroughNV = 5250,
ViewportRelativeNV = 5252,
SecondaryViewportRelativeNV = 5256,
PerPrimitiveNV = 5271,
PerViewNV = 5272,
PerVertexNV = 5273,
NonUniformEXT = 5300,
CountBuffer = 5634,
UserSemantic = 5635,
RestrictPointerEXT = 5355,
AliasedPointerEXT = 5356,
};
StringRef getDecorationName(Decoration e);
namespace AccessQualifier {
#define GET_AccessQualifier_DECL
#include "SPIRVGenTables.inc"
} // namespace AccessQualifier
enum class BuiltIn : uint32_t {
Position = 0,
PointSize = 1,
ClipDistance = 3,
CullDistance = 4,
VertexId = 5,
InstanceId = 6,
PrimitiveId = 7,
InvocationId = 8,
Layer = 9,
ViewportIndex = 10,
TessLevelOuter = 11,
TessLevelInner = 12,
TessCoord = 13,
PatchVertices = 14,
FragCoord = 15,
PointCoord = 16,
FrontFacing = 17,
SampleId = 18,
SamplePosition = 19,
SampleMask = 20,
FragDepth = 22,
HelperInvocation = 23,
NumWorkgroups = 24,
WorkgroupSize = 25,
WorkgroupId = 26,
LocalInvocationId = 27,
GlobalInvocationId = 28,
LocalInvocationIndex = 29,
WorkDim = 30,
GlobalSize = 31,
EnqueuedWorkgroupSize = 32,
GlobalOffset = 33,
GlobalLinearId = 34,
SubgroupSize = 36,
SubgroupMaxSize = 37,
NumSubgroups = 38,
NumEnqueuedSubgroups = 39,
SubgroupId = 40,
SubgroupLocalInvocationId = 41,
VertexIndex = 42,
InstanceIndex = 43,
SubgroupEqMask = 4416,
SubgroupGeMask = 4417,
SubgroupGtMask = 4418,
SubgroupLeMask = 4419,
SubgroupLtMask = 4420,
BaseVertex = 4424,
BaseInstance = 4425,
DrawIndex = 4426,
DeviceIndex = 4438,
ViewIndex = 4440,
BaryCoordNoPerspAMD = 4492,
BaryCoordNoPerspCentroidAMD = 4493,
BaryCoordNoPerspSampleAMD = 4494,
BaryCoordSmoothAMD = 4495,
BaryCoordSmoothCentroid = 4496,
BaryCoordSmoothSample = 4497,
BaryCoordPullModel = 4498,
FragStencilRefEXT = 5014,
ViewportMaskNV = 5253,
SecondaryPositionNV = 5257,
SecondaryViewportMaskNV = 5258,
PositionPerViewNV = 5261,
ViewportMaskPerViewNV = 5262,
FullyCoveredEXT = 5264,
TaskCountNV = 5274,
PrimitiveCountNV = 5275,
PrimitiveIndicesNV = 5276,
ClipDistancePerViewNV = 5277,
CullDistancePerViewNV = 5278,
LayerPerViewNV = 5279,
MeshViewCountNV = 5280,
MeshViewIndices = 5281,
BaryCoordNV = 5286,
BaryCoordNoPerspNV = 5287,
FragSizeEXT = 5292,
FragInvocationCountEXT = 5293,
LaunchIdNV = 5319,
LaunchSizeNV = 5320,
WorldRayOriginNV = 5321,
WorldRayDirectionNV = 5322,
ObjectRayOriginNV = 5323,
ObjectRayDirectionNV = 5324,
RayTminNV = 5325,
RayTmaxNV = 5326,
InstanceCustomIndexNV = 5327,
ObjectToWorldNV = 5330,
WorldToObjectNV = 5331,
HitTNV = 5332,
HitKindNV = 5333,
IncomingRayFlagsNV = 5351,
};
StringRef getBuiltInName(BuiltIn e);
namespace FunctionParameterAttribute {
#define GET_FunctionParameterAttribute_DECL
#include "SPIRVGenTables.inc"
} // namespace FunctionParameterAttribute
enum class SelectionControl : uint32_t {
None = 0x0,
Flatten = 0x1,
DontFlatten = 0x2,
};
std::string getSelectionControlName(uint32_t e);
namespace Decoration {
#define GET_Decoration_DECL
#include "SPIRVGenTables.inc"
} // namespace Decoration
enum class LoopControl : uint32_t {
None = 0x0,
Unroll = 0x1,
DontUnroll = 0x2,
DependencyInfinite = 0x4,
DependencyLength = 0x8,
MinIterations = 0x10,
MaxIterations = 0x20,
IterationMultiple = 0x40,
PeelCount = 0x80,
PartialCount = 0x100,
};
std::string getLoopControlName(uint32_t e);
namespace BuiltIn {
#define GET_BuiltIn_DECL
#include "SPIRVGenTables.inc"
} // namespace BuiltIn
enum class FunctionControl : uint32_t {
None = 0x0,
Inline = 0x1,
DontInline = 0x2,
Pure = 0x4,
Const = 0x8,
};
std::string getFunctionControlName(uint32_t e);
namespace SelectionControl {
#define GET_SelectionControl_DECL
#include "SPIRVGenTables.inc"
} // namespace SelectionControl
enum class MemorySemantics : uint32_t {
None = 0x0,
Acquire = 0x2,
Release = 0x4,
AcquireRelease = 0x8,
SequentiallyConsistent = 0x10,
UniformMemory = 0x40,
SubgroupMemory = 0x80,
WorkgroupMemory = 0x100,
CrossWorkgroupMemory = 0x200,
AtomicCounterMemory = 0x400,
ImageMemory = 0x800,
OutputMemoryKHR = 0x1000,
MakeAvailableKHR = 0x2000,
MakeVisibleKHR = 0x4000,
};
std::string getMemorySemanticsName(uint32_t e);
namespace LoopControl {
#define GET_LoopControl_DECL
#include "SPIRVGenTables.inc"
} // namespace LoopControl
enum class MemoryOperand : uint32_t {
None = 0x0,
Volatile = 0x1,
Aligned = 0x2,
Nontemporal = 0x4,
MakePointerAvailableKHR = 0x8,
MakePointerVisibleKHR = 0x10,
NonPrivatePointerKHR = 0x20,
};
std::string getMemoryOperandName(uint32_t e);
namespace FunctionControl {
#define GET_FunctionControl_DECL
#include "SPIRVGenTables.inc"
} // namespace FunctionControl
enum class Scope : uint32_t {
CrossDevice = 0,
Device = 1,
Workgroup = 2,
Subgroup = 3,
Invocation = 4,
QueueFamilyKHR = 5,
};
StringRef getScopeName(Scope e);
namespace MemorySemantics {
#define GET_MemorySemantics_DECL
#include "SPIRVGenTables.inc"
} // namespace MemorySemantics
enum class GroupOperation : uint32_t {
Reduce = 0,
InclusiveScan = 1,
ExclusiveScan = 2,
ClusteredReduce = 3,
PartitionedReduceNV = 6,
PartitionedInclusiveScanNV = 7,
PartitionedExclusiveScanNV = 8,
};
StringRef getGroupOperationName(GroupOperation e);
namespace MemoryOperand {
#define GET_MemoryOperand_DECL
#include "SPIRVGenTables.inc"
} // namespace MemoryOperand
enum class KernelEnqueueFlags : uint32_t {
NoWait = 0,
WaitKernel = 1,
WaitWorkGroup = 2,
};
StringRef getKernelEnqueueFlagsName(KernelEnqueueFlags e);
namespace Scope {
#define GET_Scope_DECL
#include "SPIRVGenTables.inc"
} // namespace Scope
enum class KernelProfilingInfo : uint32_t {
None = 0x0,
CmdExecTime = 0x1,
};
StringRef getKernelProfilingInfoName(KernelProfilingInfo e);
namespace GroupOperation {
#define GET_GroupOperation_DECL
#include "SPIRVGenTables.inc"
} // namespace GroupOperation
namespace KernelEnqueueFlags {
#define GET_KernelEnqueueFlags_DECL
#include "SPIRVGenTables.inc"
} // namespace KernelEnqueueFlags
namespace KernelProfilingInfo {
#define GET_KernelProfilingInfo_DECL
#include "SPIRVGenTables.inc"
} // namespace KernelProfilingInfo
namespace OpenCLExtInst {
#define GET_OpenCLExtInst_DECL
#include "SPIRVGenTables.inc"
} // namespace OpenCLExtInst
namespace GLSLExtInst {
#define GET_GLSLExtInst_DECL
#include "SPIRVGenTables.inc"
} // namespace GLSLExtInst
namespace Opcode {
#define GET_Opcode_DECL
#include "SPIRVGenTables.inc"
} // namespace Opcode
enum class InstructionSet : uint32_t {
OpenCL_std = 0,
@ -713,14 +202,29 @@ enum class InstructionSet : uint32_t {
SPV_AMD_shader_trinary_minmax = 2,
};
std::string getExtInstSetName(InstructionSet e);
// TODO: implement other mnemonics.
enum class Opcode : uint32_t {
InBoundsPtrAccessChain = 70,
PtrCastToGeneric = 121,
};
} // namespace SPIRV
} // namespace llvm
using CapabilityList = SmallVector<SPIRV::Capability::Capability, 8>;
using ExtensionList = SmallVector<SPIRV::Extension::Extension, 8>;
std::string
getSymbolicOperandMnemonic(SPIRV::OperandCategory::OperandCategory Category,
int32_t Value);
uint32_t
getSymbolicOperandMinVersion(SPIRV::OperandCategory::OperandCategory Category,
uint32_t Value);
uint32_t
getSymbolicOperandMaxVersion(SPIRV::OperandCategory::OperandCategory Category,
uint32_t Value);
CapabilityList
getSymbolicOperandCapabilities(SPIRV::OperandCategory::OperandCategory Category,
uint32_t Value);
ExtensionList
getSymbolicOperandExtensions(SPIRV::OperandCategory::OperandCategory Category,
uint32_t Value);
std::string getLinkStringForBuiltIn(SPIRV::BuiltIn::BuiltIn BuiltInValue);
bool getSpirvBuiltInIdByName(StringRef Name, SPIRV::BuiltIn::BuiltIn &BI);
// Return a string representation of the operands from startIndex onwards.
// Templated to allow both MachineInstr and MCInst to use the same logic.
@ -741,12 +245,11 @@ std::string getSPIRVStringOperand(const InstType &MI, unsigned StartIndex) {
if (c == 0) { // Stop if we hit a null-terminator character.
IsFinished = true;
break;
} else {
s += c; // Otherwise, append the character to the result string.
}
s += c; // Otherwise, append the character to the result string.
}
}
return s;
}
#endif // LLVM_LIB_TARGET_SPIRV_MCTARGETDESC_SPIRVBASEINFO_H
} // namespace llvm
#endif // LLVM_LIB_TARGET_SPIRV_SPIRVSYMBOLICOPERANDS_H

View File

@ -24,6 +24,7 @@
#include "llvm/Support/FormattedStream.h"
using namespace llvm;
using namespace llvm::SPIRV;
#define DEBUG_TYPE "asm-printer"
@ -89,7 +90,8 @@ void SPIRVInstPrinter::printInst(const MCInst *MI, uint64_t Address,
switch (OpCode) {
case SPIRV::OpTypeImage:
OS << ' ';
printAccessQualifier(MI, FirstVariableIndex, OS);
printSymbolicOperand<OperandCategory::AccessQualifierOperand>(
MI, FirstVariableIndex, OS);
break;
case SPIRV::OpVariable:
OS << ' ';
@ -109,7 +111,7 @@ void SPIRVInstPrinter::printInst(const MCInst *MI, uint64_t Address,
break;
}
default:
break; // printStringImm has already been handled
break; // printStringImm has already been handled.
}
} else {
// For instructions with no fixed ops or a reg/immediate as the final
@ -119,7 +121,8 @@ void SPIRVInstPrinter::printInst(const MCInst *MI, uint64_t Address,
case SPIRV::OpLoad:
case SPIRV::OpStore:
OS << ' ';
printMemoryOperand(MI, FirstVariableIndex, OS);
printSymbolicOperand<OperandCategory::MemoryOperandOperand>(
MI, FirstVariableIndex, OS);
printRemainingVariableOps(MI, FirstVariableIndex + 1, OS);
break;
case SPIRV::OpImageSampleImplicitLod:
@ -141,7 +144,8 @@ void SPIRVInstPrinter::printInst(const MCInst *MI, uint64_t Address,
case SPIRV::OpImageSparseRead:
case SPIRV::OpImageSampleFootprintNV:
OS << ' ';
printImageOperand(MI, FirstVariableIndex, OS);
printSymbolicOperand<OperandCategory::ImageOperandOperand>(
MI, FirstVariableIndex, OS);
printRemainingVariableOps(MI, NumFixedOps + 1, OS);
break;
case SPIRV::OpCopyMemory:
@ -149,9 +153,9 @@ void SPIRVInstPrinter::printInst(const MCInst *MI, uint64_t Address,
const unsigned NumOps = MI->getNumOperands();
for (unsigned i = NumFixedOps; i < NumOps; ++i) {
OS << ' ';
printMemoryOperand(MI, i, OS);
if (MI->getOperand(i).getImm() &
static_cast<unsigned>(SPIRV::MemoryOperand::Aligned)) {
printSymbolicOperand<OperandCategory::MemoryOperandOperand>(MI, i,
OS);
if (MI->getOperand(i).getImm() & MemoryOperand::Aligned) {
assert(i + 1 < NumOps && "Missing alignment operand");
OS << ' ';
printOperand(MI, i + 1, OS);
@ -198,28 +202,31 @@ void SPIRVInstPrinter::printOpDecorate(const MCInst *MI, raw_ostream &O) {
if (NumFixedOps != MI->getNumOperands()) {
auto DecOp = MI->getOperand(NumFixedOps - 1);
auto Dec = static_cast<SPIRV::Decoration>(DecOp.getImm());
auto Dec = static_cast<Decoration::Decoration>(DecOp.getImm());
O << ' ';
switch (Dec) {
case SPIRV::Decoration::BuiltIn:
printBuiltIn(MI, NumFixedOps, O);
case Decoration::BuiltIn:
printSymbolicOperand<OperandCategory::BuiltInOperand>(MI, NumFixedOps, O);
break;
case SPIRV::Decoration::UniformId:
printScope(MI, NumFixedOps, O);
case Decoration::UniformId:
printSymbolicOperand<OperandCategory::ScopeOperand>(MI, NumFixedOps, O);
break;
case SPIRV::Decoration::FuncParamAttr:
printFunctionParameterAttribute(MI, NumFixedOps, O);
case Decoration::FuncParamAttr:
printSymbolicOperand<OperandCategory::FunctionParameterAttributeOperand>(
MI, NumFixedOps, O);
break;
case SPIRV::Decoration::FPRoundingMode:
printFPRoundingMode(MI, NumFixedOps, O);
case Decoration::FPRoundingMode:
printSymbolicOperand<OperandCategory::FPRoundingModeOperand>(
MI, NumFixedOps, O);
break;
case SPIRV::Decoration::FPFastMathMode:
printFPFastMathMode(MI, NumFixedOps, O);
case Decoration::FPFastMathMode:
printSymbolicOperand<OperandCategory::FPFastMathModeOperand>(
MI, NumFixedOps, O);
break;
case SPIRV::Decoration::LinkageAttributes:
case SPIRV::Decoration::UserSemantic:
case Decoration::LinkageAttributes:
case Decoration::UserSemantic:
printStringImm(MI, NumFixedOps, O);
break;
default:
@ -288,280 +295,24 @@ void SPIRVInstPrinter::printStringImm(const MCInst *MI, unsigned OpNo,
// Check for final Op of "OpDecorate %x %stringImm %linkageAttribute".
if (MI->getOpcode() == SPIRV::OpDecorate &&
MI->getOperand(1).getImm() ==
static_cast<unsigned>(SPIRV::Decoration::LinkageAttributes)) {
static_cast<unsigned>(Decoration::LinkageAttributes)) {
O << ' ';
printLinkageType(MI, StrStartIndex, O);
printSymbolicOperand<OperandCategory::LinkageTypeOperand>(
MI, StrStartIndex, O);
break;
}
}
}
void SPIRVInstPrinter::printExtInst(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
llvm_unreachable("Unimplemented printExtInst");
void SPIRVInstPrinter::printExtension(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
llvm_unreachable("Unimplemented printExtension");
}
void SPIRVInstPrinter::printCapability(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
if (OpNo < MI->getNumOperands()) {
SPIRV::Capability e =
static_cast<SPIRV::Capability>(MI->getOperand(OpNo).getImm());
O << SPIRV::getCapabilityName(e);
}
}
void SPIRVInstPrinter::printSourceLanguage(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
if (OpNo < MI->getNumOperands()) {
SPIRV::SourceLanguage e =
static_cast<SPIRV::SourceLanguage>(MI->getOperand(OpNo).getImm());
O << SPIRV::getSourceLanguageName(e);
}
}
void SPIRVInstPrinter::printExecutionModel(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
if (OpNo < MI->getNumOperands()) {
SPIRV::ExecutionModel e =
static_cast<SPIRV::ExecutionModel>(MI->getOperand(OpNo).getImm());
O << SPIRV::getExecutionModelName(e);
}
}
void SPIRVInstPrinter::printAddressingModel(const MCInst *MI, unsigned OpNo,
template <OperandCategory::OperandCategory category>
void SPIRVInstPrinter::printSymbolicOperand(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
if (OpNo < MI->getNumOperands()) {
SPIRV::AddressingModel e =
static_cast<SPIRV::AddressingModel>(MI->getOperand(OpNo).getImm());
O << SPIRV::getAddressingModelName(e);
}
}
void SPIRVInstPrinter::printMemoryModel(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
if (OpNo < MI->getNumOperands()) {
SPIRV::MemoryModel e =
static_cast<SPIRV::MemoryModel>(MI->getOperand(OpNo).getImm());
O << SPIRV::getMemoryModelName(e);
}
}
void SPIRVInstPrinter::printExecutionMode(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
if (OpNo < MI->getNumOperands()) {
SPIRV::ExecutionMode e =
static_cast<SPIRV::ExecutionMode>(MI->getOperand(OpNo).getImm());
O << SPIRV::getExecutionModeName(e);
}
}
void SPIRVInstPrinter::printStorageClass(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
if (OpNo < MI->getNumOperands()) {
SPIRV::StorageClass e =
static_cast<SPIRV::StorageClass>(MI->getOperand(OpNo).getImm());
O << SPIRV::getStorageClassName(e);
}
}
void SPIRVInstPrinter::printDim(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
if (OpNo < MI->getNumOperands()) {
SPIRV::Dim e = static_cast<SPIRV::Dim>(MI->getOperand(OpNo).getImm());
O << SPIRV::getDimName(e);
}
}
void SPIRVInstPrinter::printSamplerAddressingMode(const MCInst *MI,
unsigned OpNo,
raw_ostream &O) {
if (OpNo < MI->getNumOperands()) {
SPIRV::SamplerAddressingMode e = static_cast<SPIRV::SamplerAddressingMode>(
MI->getOperand(OpNo).getImm());
O << SPIRV::getSamplerAddressingModeName(e);
}
}
void SPIRVInstPrinter::printSamplerFilterMode(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
if (OpNo < MI->getNumOperands()) {
SPIRV::SamplerFilterMode e =
static_cast<SPIRV::SamplerFilterMode>(MI->getOperand(OpNo).getImm());
O << SPIRV::getSamplerFilterModeName(e);
}
}
void SPIRVInstPrinter::printImageFormat(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
if (OpNo < MI->getNumOperands()) {
SPIRV::ImageFormat e =
static_cast<SPIRV::ImageFormat>(MI->getOperand(OpNo).getImm());
O << SPIRV::getImageFormatName(e);
}
}
void SPIRVInstPrinter::printImageChannelOrder(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
if (OpNo < MI->getNumOperands()) {
SPIRV::ImageChannelOrder e =
static_cast<SPIRV::ImageChannelOrder>(MI->getOperand(OpNo).getImm());
O << SPIRV::getImageChannelOrderName(e);
}
}
void SPIRVInstPrinter::printImageChannelDataType(const MCInst *MI,
unsigned OpNo,
raw_ostream &O) {
if (OpNo < MI->getNumOperands()) {
SPIRV::ImageChannelDataType e =
static_cast<SPIRV::ImageChannelDataType>(MI->getOperand(OpNo).getImm());
O << SPIRV::getImageChannelDataTypeName(e);
}
}
void SPIRVInstPrinter::printImageOperand(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
if (OpNo < MI->getNumOperands()) {
unsigned e = static_cast<unsigned>(MI->getOperand(OpNo).getImm());
O << SPIRV::getImageOperandName(e);
}
}
void SPIRVInstPrinter::printFPFastMathMode(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
if (OpNo < MI->getNumOperands()) {
unsigned e = static_cast<unsigned>(MI->getOperand(OpNo).getImm());
O << SPIRV::getFPFastMathModeName(e);
}
}
void SPIRVInstPrinter::printFPRoundingMode(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
if (OpNo < MI->getNumOperands()) {
SPIRV::FPRoundingMode e =
static_cast<SPIRV::FPRoundingMode>(MI->getOperand(OpNo).getImm());
O << SPIRV::getFPRoundingModeName(e);
}
}
void SPIRVInstPrinter::printLinkageType(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
if (OpNo < MI->getNumOperands()) {
SPIRV::LinkageType e =
static_cast<SPIRV::LinkageType>(MI->getOperand(OpNo).getImm());
O << SPIRV::getLinkageTypeName(e);
}
}
void SPIRVInstPrinter::printAccessQualifier(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
if (OpNo < MI->getNumOperands()) {
SPIRV::AccessQualifier e =
static_cast<SPIRV::AccessQualifier>(MI->getOperand(OpNo).getImm());
O << SPIRV::getAccessQualifierName(e);
}
}
void SPIRVInstPrinter::printFunctionParameterAttribute(const MCInst *MI,
unsigned OpNo,
raw_ostream &O) {
if (OpNo < MI->getNumOperands()) {
SPIRV::FunctionParameterAttribute e =
static_cast<SPIRV::FunctionParameterAttribute>(
MI->getOperand(OpNo).getImm());
O << SPIRV::getFunctionParameterAttributeName(e);
}
}
void SPIRVInstPrinter::printDecoration(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
if (OpNo < MI->getNumOperands()) {
SPIRV::Decoration e =
static_cast<SPIRV::Decoration>(MI->getOperand(OpNo).getImm());
O << SPIRV::getDecorationName(e);
}
}
void SPIRVInstPrinter::printBuiltIn(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
if (OpNo < MI->getNumOperands()) {
SPIRV::BuiltIn e =
static_cast<SPIRV::BuiltIn>(MI->getOperand(OpNo).getImm());
O << SPIRV::getBuiltInName(e);
}
}
void SPIRVInstPrinter::printSelectionControl(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
if (OpNo < MI->getNumOperands()) {
unsigned e = static_cast<unsigned>(MI->getOperand(OpNo).getImm());
O << SPIRV::getSelectionControlName(e);
}
}
void SPIRVInstPrinter::printLoopControl(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
if (OpNo < MI->getNumOperands()) {
unsigned e = static_cast<unsigned>(MI->getOperand(OpNo).getImm());
O << SPIRV::getLoopControlName(e);
}
}
void SPIRVInstPrinter::printFunctionControl(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
if (OpNo < MI->getNumOperands()) {
unsigned e = static_cast<unsigned>(MI->getOperand(OpNo).getImm());
O << SPIRV::getFunctionControlName(e);
}
}
void SPIRVInstPrinter::printMemorySemantics(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
if (OpNo < MI->getNumOperands()) {
unsigned e = static_cast<unsigned>(MI->getOperand(OpNo).getImm());
O << SPIRV::getMemorySemanticsName(e);
}
}
void SPIRVInstPrinter::printMemoryOperand(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
if (OpNo < MI->getNumOperands()) {
unsigned e = static_cast<unsigned>(MI->getOperand(OpNo).getImm());
O << SPIRV::getMemoryOperandName(e);
}
}
void SPIRVInstPrinter::printScope(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
if (OpNo < MI->getNumOperands()) {
SPIRV::Scope e = static_cast<SPIRV::Scope>(MI->getOperand(OpNo).getImm());
O << SPIRV::getScopeName(e);
}
}
void SPIRVInstPrinter::printGroupOperation(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
if (OpNo < MI->getNumOperands()) {
SPIRV::GroupOperation e =
static_cast<SPIRV::GroupOperation>(MI->getOperand(OpNo).getImm());
O << SPIRV::getGroupOperationName(e);
}
}
void SPIRVInstPrinter::printKernelEnqueueFlags(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
if (OpNo < MI->getNumOperands()) {
SPIRV::KernelEnqueueFlags e =
static_cast<SPIRV::KernelEnqueueFlags>(MI->getOperand(OpNo).getImm());
O << SPIRV::getKernelEnqueueFlagsName(e);
}
}
void SPIRVInstPrinter::printKernelProfilingInfo(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
if (OpNo < MI->getNumOperands()) {
SPIRV::KernelProfilingInfo e =
static_cast<SPIRV::KernelProfilingInfo>(MI->getOperand(OpNo).getImm());
O << SPIRV::getKernelProfilingInfoName(e);
O << getSymbolicOperandMnemonic(category, MI->getOperand(OpNo).getImm());
}
}

View File

@ -13,6 +13,7 @@
#ifndef LLVM_LIB_TARGET_SPIRV_INSTPRINTER_SPIRVINSTPRINTER_H
#define LLVM_LIB_TARGET_SPIRV_INSTPRINTER_SPIRVINSTPRINTER_H
#include "MCTargetDesc/SPIRVBaseInfo.h"
#include "llvm/MC/MCInstPrinter.h"
namespace llvm {
@ -38,52 +39,10 @@ public:
void printOpConstantVarOps(const MCInst *MI, unsigned StartIndex,
raw_ostream &O);
void printExtInst(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printExtension(const MCInst *MI, unsigned OpNo, raw_ostream &O);
template <SPIRV::OperandCategory::OperandCategory category>
void printSymbolicOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
// SPIR-V enumerations printing.
void printCapability(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printSourceLanguage(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printExecutionModel(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printAddressingModel(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printMemoryModel(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printExecutionMode(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printStorageClass(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printDim(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printSamplerAddressingMode(const MCInst *MI, unsigned OpNo,
raw_ostream &O);
void printSamplerFilterMode(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printImageFormat(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printImageChannelOrder(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printImageChannelDataType(const MCInst *MI, unsigned OpNo,
raw_ostream &O);
void printImageOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printFPFastMathMode(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printFPRoundingMode(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printLinkageType(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printAccessQualifier(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printFunctionParameterAttribute(const MCInst *MI, unsigned OpNo,
raw_ostream &O);
void printDecoration(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printBuiltIn(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printSelectionControl(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printLoopControl(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printFunctionControl(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printMemorySemantics(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printMemoryOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printScope(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printGroupOperation(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printKernelEnqueueFlags(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printKernelProfilingInfo(const MCInst *MI, unsigned OpNo,
raw_ostream &O);
// Autogenerated by tblgen.
std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override;
void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O);

View File

@ -64,7 +64,7 @@ public:
void outputOpFunctionEnd();
void outputExtFuncDecls();
void outputExecutionModeFromMDNode(Register Reg, MDNode *Node,
SPIRV::ExecutionMode EM);
SPIRV::ExecutionMode::ExecutionMode EM);
void outputExecutionMode(const Module &M);
void outputAnnotations(const Module &M);
void outputModuleSections();
@ -291,7 +291,8 @@ void SPIRVAsmPrinter::outputEntryPoints() {
DenseSet<Register> InterfaceIDs;
for (MachineInstr *MI : MAI->GlobalVarList) {
assert(MI->getOpcode() == SPIRV::OpVariable);
auto SC = static_cast<SPIRV::StorageClass>(MI->getOperand(2).getImm());
auto SC = static_cast<SPIRV::StorageClass::StorageClass>(
MI->getOperand(2).getImm());
// Before version 1.4, the interface's storage classes are limited to
// the Input and Output storage classes. Starting with version 1.4,
// the interface's storage classes are all storage classes used in
@ -375,8 +376,8 @@ static void addOpsFromMDNode(MDNode *MDN, MCInst &Inst,
}
}
void SPIRVAsmPrinter::outputExecutionModeFromMDNode(Register Reg, MDNode *Node,
SPIRV::ExecutionMode EM) {
void SPIRVAsmPrinter::outputExecutionModeFromMDNode(
Register Reg, MDNode *Node, SPIRV::ExecutionMode::ExecutionMode EM) {
MCInst Inst;
Inst.setOpcode(SPIRV::OpExecutionMode);
Inst.addOperand(MCOperand::createReg(Reg));

View File

@ -132,7 +132,8 @@ bool SPIRVCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
if (VRegs[i].size() > 1)
return false;
Type *ArgTy = FTy->getParamType(i);
SPIRV::AccessQualifier AQ = SPIRV::AccessQualifier::ReadWrite;
SPIRV::AccessQualifier::AccessQualifier AQ =
SPIRV::AccessQualifier::ReadWrite;
MDNode *Node = F.getMetadata("kernel_arg_access_qual");
if (Node && i < Node->getNumOperands()) {
StringRef AQString = cast<MDString>(Node->getOperand(i))->getString();
@ -192,7 +193,8 @@ bool SPIRVCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
assert(MD2 && "Metadata operand is expected");
ConstantInt *Const = getConstInt(MD2, 0);
assert(Const && "MDOperand should be ConstantInt");
auto Dec = static_cast<SPIRV::Decoration>(Const->getZExtValue());
auto Dec =
static_cast<SPIRV::Decoration::Decoration>(Const->getZExtValue());
std::vector<uint32_t> DecVec;
for (unsigned j = 1; j < MD2->getNumOperands(); j++) {
ConstantInt *Const = getConstInt(MD2, j);

View File

@ -1,51 +0,0 @@
//===-- SPIRVEnums.td - Describe SPIRV Enum Operands -------*- tablegen -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// All SPIRV enums defined in SPIRVBaseInfo.h should have a corresponding enum
// operand here. This enables the correct PrintMethod to be defined so
// its name or mask bits can be automatically printed in SPIRVInstPrinter
// when referred to in SPIRVInstrInfo.td.
//
//===----------------------------------------------------------------------===//
class EnumOperand<string Name> : Operand<i32>{
let PrintMethod = "print"#Name;
}
def ExtInst : EnumOperand<"ExtInst">;
def Capability : EnumOperand<"Capability">;
def SourceLanguage : EnumOperand<"SourceLanguage">;
def ExecutionModel : EnumOperand<"ExecutionModel">;
def AddressingModel : EnumOperand<"AddressingModel">;
def MemoryModel : EnumOperand<"MemoryModel">;
def ExecutionMode : EnumOperand<"ExecutionMode">;
def StorageClass : EnumOperand<"StorageClass">;
def Dim : EnumOperand<"Dim">;
def SamplerAddressingMode : EnumOperand<"SamplerAddressingMode">;
def SamplerFilterMode : EnumOperand<"SamplerFilterMode">;
def ImageFormat : EnumOperand<"ImageFormat">;
def ImageChannelOrder : EnumOperand<"ImageChannelOrder">;
def ImageChannelDataType : EnumOperand<"ImageChannelDataType">;
def ImageOperand : EnumOperand<"ImageOperand">;
def FPFastMathMode : EnumOperand<"FPFastMathMode">;
def FProundingMode : EnumOperand<"FPRoundingMode">;
def LinkageType : EnumOperand<"LinkageType">;
def AccessQualifier : EnumOperand<"AccessQualifier">;
def FunctionParameterAttribute : EnumOperand<"FunctionParameterAttribute">;
def Decoration : EnumOperand<"Decoration">;
def Builtin : EnumOperand<"Builtin">;
def SelectionControl: EnumOperand<"SelectionControl">;
def LoopControl: EnumOperand<"LoopControl">;
def FunctionControl : EnumOperand<"FunctionControl">;
def MemorySemantics : EnumOperand<"MemorySemantics">;
def MemoryOperand : EnumOperand<"MemoryOperand">;
def Scope : EnumOperand<"Scope">;
def GroupOperation : EnumOperand<"GroupOperation">;
def KernelEnqueueFlags : EnumOperand<"KernelEnqueueFlags">;
def KernelProfilingInfo : EnumOperand<"KernelProfilingInfo">;

View File

@ -44,7 +44,7 @@ SPIRVType *SPIRVGlobalRegistry::assignVectTypeToVReg(
SPIRVType *SPIRVGlobalRegistry::assignTypeToVReg(
const Type *Type, Register VReg, MachineIRBuilder &MIRBuilder,
SPIRV::AccessQualifier AccessQual, bool EmitIR) {
SPIRV::AccessQualifier::AccessQualifier AccessQual, bool EmitIR) {
SPIRVType *SpirvType =
getOrCreateSPIRVType(Type, MIRBuilder, AccessQual, EmitIR);
@ -296,9 +296,9 @@ SPIRVGlobalRegistry::getOrCreateConsIntVector(uint64_t Val, MachineInstr &I,
Register SPIRVGlobalRegistry::buildGlobalVariable(
Register ResVReg, SPIRVType *BaseType, StringRef Name,
const GlobalValue *GV, SPIRV::StorageClass Storage,
const GlobalValue *GV, SPIRV::StorageClass::StorageClass Storage,
const MachineInstr *Init, bool IsConst, bool HasLinkageTy,
SPIRV::LinkageType LinkageType, MachineIRBuilder &MIRBuilder,
SPIRV::LinkageType::LinkageType LinkageType, MachineIRBuilder &MIRBuilder,
bool IsInstSelector) {
const GlobalVariable *GVar = nullptr;
if (GV)
@ -439,10 +439,9 @@ static bool isSpecialType(const Type *Ty) {
return false;
}
SPIRVType *SPIRVGlobalRegistry::getOpTypePointer(SPIRV::StorageClass SC,
SPIRVType *ElemType,
MachineIRBuilder &MIRBuilder,
Register Reg) {
SPIRVType *SPIRVGlobalRegistry::getOpTypePointer(
SPIRV::StorageClass::StorageClass SC, SPIRVType *ElemType,
MachineIRBuilder &MIRBuilder, Register Reg) {
if (!Reg.isValid())
Reg = createTypeVReg(MIRBuilder);
return MIRBuilder.buildInstr(SPIRV::OpTypePointer)
@ -451,9 +450,8 @@ SPIRVType *SPIRVGlobalRegistry::getOpTypePointer(SPIRV::StorageClass SC,
.addUse(getSPIRVTypeID(ElemType));
}
SPIRVType *
SPIRVGlobalRegistry::getOpTypeForwardPointer(SPIRV::StorageClass SC,
MachineIRBuilder &MIRBuilder) {
SPIRVType *SPIRVGlobalRegistry::getOpTypeForwardPointer(
SPIRV::StorageClass::StorageClass SC, MachineIRBuilder &MIRBuilder) {
return MIRBuilder.buildInstr(SPIRV::OpTypeForwardPointer)
.addUse(createTypeVReg(MIRBuilder))
.addImm(static_cast<uint32_t>(SC));
@ -481,10 +479,9 @@ SPIRVType *SPIRVGlobalRegistry::getOrCreateOpTypeFunctionWithArgs(
return finishCreatingSPIRVType(Ty, SpirvType);
}
SPIRVType *SPIRVGlobalRegistry::findSPIRVType(const Type *Ty,
MachineIRBuilder &MIRBuilder,
SPIRV::AccessQualifier AccQual,
bool EmitIR) {
SPIRVType *SPIRVGlobalRegistry::findSPIRVType(
const Type *Ty, MachineIRBuilder &MIRBuilder,
SPIRV::AccessQualifier::AccessQualifier AccQual, bool EmitIR) {
Register Reg = DT.find(Ty, &MIRBuilder.getMF());
if (Reg.isValid())
return getSPIRVTypeForVReg(Reg);
@ -500,10 +497,9 @@ Register SPIRVGlobalRegistry::getSPIRVTypeID(const SPIRVType *SpirvType) const {
return SpirvType->defs().begin()->getReg();
}
SPIRVType *SPIRVGlobalRegistry::createSPIRVType(const Type *Ty,
MachineIRBuilder &MIRBuilder,
SPIRV::AccessQualifier AccQual,
bool EmitIR) {
SPIRVType *SPIRVGlobalRegistry::createSPIRVType(
const Type *Ty, MachineIRBuilder &MIRBuilder,
SPIRV::AccessQualifier::AccessQualifier AccQual, bool EmitIR) {
assert(!isSpecialType(Ty));
auto &TypeToSPIRVTypeMap = DT.getTypes()->getAllUses();
auto t = TypeToSPIRVTypeMap.find(Ty);
@ -577,7 +573,7 @@ SPIRVType *SPIRVGlobalRegistry::createSPIRVType(const Type *Ty,
SPIRVType *SPIRVGlobalRegistry::restOfCreateSPIRVType(
const Type *Ty, MachineIRBuilder &MIRBuilder,
SPIRV::AccessQualifier AccessQual, bool EmitIR) {
SPIRV::AccessQualifier::AccessQualifier AccessQual, bool EmitIR) {
if (TypesInProcessing.count(Ty) && !Ty->isPointerTy())
return nullptr;
TypesInProcessing.insert(Ty);
@ -607,7 +603,7 @@ SPIRVType *SPIRVGlobalRegistry::getSPIRVTypeForVReg(Register VReg) const {
SPIRVType *SPIRVGlobalRegistry::getOrCreateSPIRVType(
const Type *Ty, MachineIRBuilder &MIRBuilder,
SPIRV::AccessQualifier AccessQual, bool EmitIR) {
SPIRV::AccessQualifier::AccessQualifier AccessQual, bool EmitIR) {
Register Reg = DT.find(Ty, &MIRBuilder.getMF());
if (Reg.isValid())
return getSPIRVTypeForVReg(Reg);
@ -675,12 +671,13 @@ bool SPIRVGlobalRegistry::isScalarOrVectorSigned(const SPIRVType *Type) const {
llvm_unreachable("Attempting to get sign of non-integer type.");
}
SPIRV::StorageClass
SPIRV::StorageClass::StorageClass
SPIRVGlobalRegistry::getPointerStorageClass(Register VReg) const {
SPIRVType *Type = getSPIRVTypeForVReg(VReg);
assert(Type && Type->getOpcode() == SPIRV::OpTypePointer &&
Type->getOperand(1).isImm() && "Pointer type is expected");
return static_cast<SPIRV::StorageClass>(Type->getOperand(1).getImm());
return static_cast<SPIRV::StorageClass::StorageClass>(
Type->getOperand(1).getImm());
}
SPIRVType *
@ -758,10 +755,9 @@ SPIRVType *SPIRVGlobalRegistry::getOrCreateSPIRVVectorType(
return finishCreatingSPIRVType(LLVMTy, MIB);
}
SPIRVType *
SPIRVGlobalRegistry::getOrCreateSPIRVPointerType(SPIRVType *BaseType,
MachineIRBuilder &MIRBuilder,
SPIRV::StorageClass SClass) {
SPIRVType *SPIRVGlobalRegistry::getOrCreateSPIRVPointerType(
SPIRVType *BaseType, MachineIRBuilder &MIRBuilder,
SPIRV::StorageClass::StorageClass SClass) {
return getOrCreateSPIRVType(
PointerType::get(const_cast<Type *>(getTypeForSPIRVType(BaseType)),
storageClassToAddressSpace(SClass)),
@ -770,7 +766,7 @@ SPIRVGlobalRegistry::getOrCreateSPIRVPointerType(SPIRVType *BaseType,
SPIRVType *SPIRVGlobalRegistry::getOrCreateSPIRVPointerType(
SPIRVType *BaseType, MachineInstr &I, const SPIRVInstrInfo &TII,
SPIRV::StorageClass SC) {
SPIRV::StorageClass::StorageClass SC) {
Type *LLVMTy =
PointerType::get(const_cast<Type *>(getTypeForSPIRVType(BaseType)),
storageClassToAddressSpace(SC));

View File

@ -45,18 +45,18 @@ class SPIRVGlobalRegistry {
const unsigned PointerSize;
// Add a new OpTypeXXX instruction without checking for duplicates.
SPIRVType *createSPIRVType(const Type *Type, MachineIRBuilder &MIRBuilder,
SPIRV::AccessQualifier::AccessQualifier AQ =
SPIRV::AccessQualifier::ReadWrite,
bool EmitIR = true);
SPIRVType *findSPIRVType(const Type *Ty, MachineIRBuilder &MIRBuilder,
SPIRV::AccessQualifier::AccessQualifier accessQual =
SPIRV::AccessQualifier::ReadWrite,
bool EmitIR = true);
SPIRVType *
createSPIRVType(const Type *Type, MachineIRBuilder &MIRBuilder,
SPIRV::AccessQualifier AQ = SPIRV::AccessQualifier::ReadWrite,
bool EmitIR = true);
SPIRVType *findSPIRVType(
const Type *Ty, MachineIRBuilder &MIRBuilder,
SPIRV::AccessQualifier accessQual = SPIRV::AccessQualifier::ReadWrite,
bool EmitIR = true);
SPIRVType *restOfCreateSPIRVType(const Type *Type,
MachineIRBuilder &MIRBuilder,
SPIRV::AccessQualifier AccessQual,
bool EmitIR);
restOfCreateSPIRVType(const Type *Type, MachineIRBuilder &MIRBuilder,
SPIRV::AccessQualifier::AccessQualifier AccessQual,
bool EmitIR);
public:
SPIRVGlobalRegistry(unsigned PointerSize);
@ -98,10 +98,11 @@ public:
// Get or create a SPIR-V type corresponding the given LLVM IR type,
// and map it to the given VReg by creating an ASSIGN_TYPE instruction.
SPIRVType *assignTypeToVReg(
const Type *Type, Register VReg, MachineIRBuilder &MIRBuilder,
SPIRV::AccessQualifier AQ = SPIRV::AccessQualifier::ReadWrite,
bool EmitIR = true);
SPIRVType *assignTypeToVReg(const Type *Type, Register VReg,
MachineIRBuilder &MIRBuilder,
SPIRV::AccessQualifier::AccessQualifier AQ =
SPIRV::AccessQualifier::ReadWrite,
bool EmitIR = true);
SPIRVType *assignIntTypeToVReg(unsigned BitWidth, Register VReg,
MachineInstr &I, const SPIRVInstrInfo &TII);
SPIRVType *assignVectTypeToVReg(SPIRVType *BaseType, unsigned NumElements,
@ -118,10 +119,11 @@ public:
// EmitIR controls if we emit GMIR or SPV constants (e.g. for array sizes)
// because this method may be called from InstructionSelector and we don't
// want to emit extra IR instructions there.
SPIRVType *getOrCreateSPIRVType(
const Type *Type, MachineIRBuilder &MIRBuilder,
SPIRV::AccessQualifier AQ = SPIRV::AccessQualifier::ReadWrite,
bool EmitIR = true);
SPIRVType *getOrCreateSPIRVType(const Type *Type,
MachineIRBuilder &MIRBuilder,
SPIRV::AccessQualifier::AccessQualifier AQ =
SPIRV::AccessQualifier::ReadWrite,
bool EmitIR = true);
const Type *getTypeForSPIRVType(const SPIRVType *Ty) const {
auto Res = SPIRVToLLVMType.find(Ty);
@ -159,7 +161,7 @@ public:
bool isScalarOrVectorSigned(const SPIRVType *Type) const;
// Gets the storage class of the pointer type assigned to this vreg.
SPIRV::StorageClass getPointerStorageClass(Register VReg) const;
SPIRV::StorageClass::StorageClass getPointerStorageClass(Register VReg) const;
// Return the number of bits SPIR-V pointers and size_t variables require.
unsigned getPointerSize() const { return PointerSize; }
@ -186,10 +188,11 @@ private:
SPIRVType *getOpTypeStruct(const StructType *Ty, MachineIRBuilder &MIRBuilder,
bool EmitIR = true);
SPIRVType *getOpTypePointer(SPIRV::StorageClass SC, SPIRVType *ElemType,
MachineIRBuilder &MIRBuilder, Register Reg);
SPIRVType *getOpTypePointer(SPIRV::StorageClass::StorageClass SC,
SPIRVType *ElemType, MachineIRBuilder &MIRBuilder,
Register Reg);
SPIRVType *getOpTypeForwardPointer(SPIRV::StorageClass SC,
SPIRVType *getOpTypeForwardPointer(SPIRV::StorageClass::StorageClass SC,
MachineIRBuilder &MIRBuilder);
SPIRVType *getOpTypeFunction(SPIRVType *RetType,
@ -212,12 +215,14 @@ public:
const SPIRVInstrInfo &TII);
Register getOrCreateUndef(MachineInstr &I, SPIRVType *SpvType,
const SPIRVInstrInfo &TII);
Register
buildGlobalVariable(Register Reg, SPIRVType *BaseType, StringRef Name,
const GlobalValue *GV, SPIRV::StorageClass Storage,
const MachineInstr *Init, bool IsConst, bool HasLinkageTy,
SPIRV::LinkageType LinkageType,
MachineIRBuilder &MIRBuilder, bool IsInstSelector);
Register buildGlobalVariable(Register Reg, SPIRVType *BaseType,
StringRef Name, const GlobalValue *GV,
SPIRV::StorageClass::StorageClass Storage,
const MachineInstr *Init, bool IsConst,
bool HasLinkageTy,
SPIRV::LinkageType::LinkageType LinkageType,
MachineIRBuilder &MIRBuilder,
bool IsInstSelector);
// Convenient helpers for getting types with check for duplicates.
SPIRVType *getOrCreateSPIRVIntegerType(unsigned BitWidth,
@ -235,10 +240,10 @@ public:
const SPIRVInstrInfo &TII);
SPIRVType *getOrCreateSPIRVPointerType(
SPIRVType *BaseType, MachineIRBuilder &MIRBuilder,
SPIRV::StorageClass SClass = SPIRV::StorageClass::Function);
SPIRV::StorageClass::StorageClass SClass = SPIRV::StorageClass::Function);
SPIRVType *getOrCreateSPIRVPointerType(
SPIRVType *BaseType, MachineInstr &I, const SPIRVInstrInfo &TII,
SPIRV::StorageClass SClass = SPIRV::StorageClass::Function);
SPIRV::StorageClass::StorageClass SClass = SPIRV::StorageClass::Function);
SPIRVType *getOrCreateOpTypeFunctionWithArgs(
const Type *Ty, SPIRVType *RetType,
const SmallVectorImpl<SPIRVType *> &ArgTypes,

View File

@ -11,7 +11,7 @@
//===----------------------------------------------------------------------===//
include "SPIRVInstrFormats.td"
include "SPIRVEnums.td"
include "SPIRVSymbolicOperands.td"
// Codegen only metadata instructions
let isCodeGenOnly=1 in {
@ -131,7 +131,7 @@ def OpMemberDecorateString: Op<5633, (outs),
def OpExtension: Op<10, (outs), (ins StringImm:$name, variable_ops), "OpExtension $name">;
def OpExtInstImport: Op<11, (outs ID:$res), (ins StringImm:$extInstsName, variable_ops),
"$res = OpExtInstImport $extInstsName">;
def OpExtInst: Op<12, (outs ID:$res), (ins TYPE:$ty, ID:$set, ExtInst:$inst, variable_ops),
def OpExtInst: Op<12, (outs ID:$res), (ins TYPE:$ty, ID:$set, Extension:$inst, variable_ops),
"$res = OpExtInst $ty $set $inst">;
// 3.42.5 Mode-Setting Instructions

View File

@ -413,7 +413,7 @@ bool SPIRVInstructionSelector::selectUnOp(Register ResVReg,
Opcode);
}
static SPIRV::Scope getScope(SyncScope::ID Ord) {
static SPIRV::Scope::Scope getScope(SyncScope::ID Ord) {
switch (Ord) {
case SyncScope::SingleThread:
return SPIRV::Scope::Invocation;
@ -616,7 +616,7 @@ bool SPIRVInstructionSelector::selectAtomicCmpXchg(Register ResVReg,
return Result;
}
static bool isGenericCastablePtr(SPIRV::StorageClass SC) {
static bool isGenericCastablePtr(SPIRV::StorageClass::StorageClass SC) {
switch (SC) {
case SPIRV::StorageClass::Workgroup:
case SPIRV::StorageClass::CrossWorkgroup:
@ -658,8 +658,8 @@ bool SPIRVInstructionSelector::selectAddrSpaceCast(Register ResVReg,
}
Register SrcPtr = I.getOperand(1).getReg();
SPIRVType *SrcPtrTy = GR.getSPIRVTypeForVReg(SrcPtr);
SPIRV::StorageClass SrcSC = GR.getPointerStorageClass(SrcPtr);
SPIRV::StorageClass DstSC = GR.getPointerStorageClass(ResVReg);
SPIRV::StorageClass::StorageClass SrcSC = GR.getPointerStorageClass(SrcPtr);
SPIRV::StorageClass::StorageClass DstSC = GR.getPointerStorageClass(ResVReg);
// Casting from an eligable pointer to Generic.
if (DstSC == SPIRV::StorageClass::Generic && isGenericCastablePtr(SrcSC))
@ -1342,10 +1342,11 @@ bool SPIRVInstructionSelector::selectGlobalValue(
return true;
unsigned AddrSpace = GV->getAddressSpace();
SPIRV::StorageClass Storage = addressSpaceToStorageClass(AddrSpace);
SPIRV::StorageClass::StorageClass Storage =
addressSpaceToStorageClass(AddrSpace);
bool HasLnkTy = GV->getLinkage() != GlobalValue::InternalLinkage &&
Storage != SPIRV::StorageClass::Function;
SPIRV::LinkageType LnkType =
SPIRV::LinkageType::LinkageType LnkType =
(GV->isDeclaration() || GV->hasAvailableExternallyLinkage())
? SPIRV::LinkageType::Import
: SPIRV::LinkageType::Export;

View File

@ -65,8 +65,10 @@ void SPIRVModuleAnalysis::setBaseInfo(const Module &M) {
// TODO: determine memory model and source language from the configuratoin.
if (auto MemModel = M.getNamedMetadata("spirv.MemoryModel")) {
auto MemMD = MemModel->getOperand(0);
MAI.Addr = static_cast<SPIRV::AddressingModel>(getMetadataUInt(MemMD, 0));
MAI.Mem = static_cast<SPIRV::MemoryModel>(getMetadataUInt(MemMD, 1));
MAI.Addr = static_cast<SPIRV::AddressingModel::AddressingModel>(
getMetadataUInt(MemMD, 0));
MAI.Mem =
static_cast<SPIRV::MemoryModel::MemoryModel>(getMetadataUInt(MemMD, 1));
} else {
MAI.Mem = SPIRV::MemoryModel::OpenCL;
unsigned PtrSize = ST->getPointerSize();

View File

@ -48,9 +48,9 @@ using RegisterAliasMapTy =
// The struct contains results of the module analysis and methods
// to access them.
struct ModuleAnalysisInfo {
SPIRV::MemoryModel Mem;
SPIRV::AddressingModel Addr;
SPIRV::SourceLanguage SrcLang;
SPIRV::MemoryModel::MemoryModel Mem;
SPIRV::AddressingModel::AddressingModel Addr;
SPIRV::SourceLanguage::SourceLanguage SrcLang;
unsigned SrcLangVersion;
StringSet<> SrcExt;
// Maps ExtInstSet to corresponding ID register.

File diff suppressed because it is too large Load Diff

View File

@ -20,7 +20,7 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/IR/IntrinsicsSPIRV.h"
using namespace llvm;
namespace llvm {
// The following functions are used to add these string literals as a series of
// 32-bit integer operands with the correct format, and unpack them if necessary
@ -114,7 +114,7 @@ static void finishBuildOpDecorate(MachineInstrBuilder &MIB,
}
void buildOpDecorate(Register Reg, MachineIRBuilder &MIRBuilder,
llvm::SPIRV::Decoration Dec,
SPIRV::Decoration::Decoration Dec,
const std::vector<uint32_t> &DecArgs, StringRef StrImm) {
auto MIB = MIRBuilder.buildInstr(SPIRV::OpDecorate)
.addUse(Reg)
@ -123,7 +123,7 @@ void buildOpDecorate(Register Reg, MachineIRBuilder &MIRBuilder,
}
void buildOpDecorate(Register Reg, MachineInstr &I, const SPIRVInstrInfo &TII,
llvm::SPIRV::Decoration Dec,
SPIRV::Decoration::Decoration Dec,
const std::vector<uint32_t> &DecArgs, StringRef StrImm) {
MachineBasicBlock &MBB = *I.getParent();
auto MIB = BuildMI(MBB, I, I.getDebugLoc(), TII.get(SPIRV::OpDecorate))
@ -134,7 +134,7 @@ void buildOpDecorate(Register Reg, MachineInstr &I, const SPIRVInstrInfo &TII,
// TODO: maybe the following two functions should be handled in the subtarget
// to allow for different OpenCL vs Vulkan handling.
unsigned storageClassToAddressSpace(SPIRV::StorageClass SC) {
unsigned storageClassToAddressSpace(SPIRV::StorageClass::StorageClass SC) {
switch (SC) {
case SPIRV::StorageClass::Function:
return 0;
@ -153,7 +153,8 @@ unsigned storageClassToAddressSpace(SPIRV::StorageClass SC) {
}
}
SPIRV::StorageClass addressSpaceToStorageClass(unsigned AddrSpace) {
SPIRV::StorageClass::StorageClass
addressSpaceToStorageClass(unsigned AddrSpace) {
switch (AddrSpace) {
case 0:
return SPIRV::StorageClass::Function;
@ -172,7 +173,8 @@ SPIRV::StorageClass addressSpaceToStorageClass(unsigned AddrSpace) {
}
}
SPIRV::MemorySemantics getMemSemanticsForStorageClass(SPIRV::StorageClass SC) {
SPIRV::MemorySemantics::MemorySemantics
getMemSemanticsForStorageClass(SPIRV::StorageClass::StorageClass SC) {
switch (SC) {
case SPIRV::StorageClass::StorageBuffer:
case SPIRV::StorageClass::Uniform:
@ -190,7 +192,7 @@ SPIRV::MemorySemantics getMemSemanticsForStorageClass(SPIRV::StorageClass SC) {
}
}
SPIRV::MemorySemantics getMemSemantics(AtomicOrdering Ord) {
SPIRV::MemorySemantics::MemorySemantics getMemSemantics(AtomicOrdering Ord) {
switch (Ord) {
case AtomicOrdering::Acquire:
return SPIRV::MemorySemantics::Acquire;
@ -236,3 +238,4 @@ bool isSpvIntrinsic(MachineInstr &MI, Intrinsic::ID IntrinsicID) {
Type *getMDOperandAsType(const MDNode *N, unsigned I) {
return cast<ValueAsMetadata>(N->getOperand(I))->getType();
}
} // namespace llvm

View File

@ -27,63 +27,61 @@ class MachineRegisterInfo;
class Register;
class StringRef;
class SPIRVInstrInfo;
} // namespace llvm
// Add the given string as a series of integer operand, inserting null
// terminators and padding to make sure the operands all have 32-bit
// little-endian words.
void addStringImm(const llvm::StringRef &Str, llvm::MCInst &Inst);
void addStringImm(const llvm::StringRef &Str, llvm::MachineInstrBuilder &MIB);
void addStringImm(const llvm::StringRef &Str, llvm::IRBuilder<> &B,
std::vector<llvm::Value *> &Args);
void addStringImm(const StringRef &Str, MCInst &Inst);
void addStringImm(const StringRef &Str, MachineInstrBuilder &MIB);
void addStringImm(const StringRef &Str, IRBuilder<> &B,
std::vector<Value *> &Args);
// Read the series of integer operands back as a null-terminated string using
// the reverse of the logic in addStringImm.
std::string getStringImm(const llvm::MachineInstr &MI, unsigned StartIndex);
std::string getStringImm(const MachineInstr &MI, unsigned StartIndex);
// Add the given numerical immediate to MIB.
void addNumImm(const llvm::APInt &Imm, llvm::MachineInstrBuilder &MIB);
void addNumImm(const APInt &Imm, MachineInstrBuilder &MIB);
// Add an OpName instruction for the given target register.
void buildOpName(llvm::Register Target, const llvm::StringRef &Name,
llvm::MachineIRBuilder &MIRBuilder);
void buildOpName(Register Target, const StringRef &Name,
MachineIRBuilder &MIRBuilder);
// Add an OpDecorate instruction for the given Reg.
void buildOpDecorate(llvm::Register Reg, llvm::MachineIRBuilder &MIRBuilder,
llvm::SPIRV::Decoration Dec,
void buildOpDecorate(Register Reg, MachineIRBuilder &MIRBuilder,
SPIRV::Decoration::Decoration Dec,
const std::vector<uint32_t> &DecArgs,
llvm::StringRef StrImm = "");
void buildOpDecorate(llvm::Register Reg, llvm::MachineInstr &I,
const llvm::SPIRVInstrInfo &TII,
llvm::SPIRV::Decoration Dec,
StringRef StrImm = "");
void buildOpDecorate(Register Reg, MachineInstr &I, const SPIRVInstrInfo &TII,
SPIRV::Decoration::Decoration Dec,
const std::vector<uint32_t> &DecArgs,
llvm::StringRef StrImm = "");
StringRef StrImm = "");
// Convert a SPIR-V storage class to the corresponding LLVM IR address space.
unsigned storageClassToAddressSpace(llvm::SPIRV::StorageClass SC);
unsigned storageClassToAddressSpace(SPIRV::StorageClass::StorageClass SC);
// Convert an LLVM IR address space to a SPIR-V storage class.
llvm::SPIRV::StorageClass addressSpaceToStorageClass(unsigned AddrSpace);
SPIRV::StorageClass::StorageClass
addressSpaceToStorageClass(unsigned AddrSpace);
llvm::SPIRV::MemorySemantics
getMemSemanticsForStorageClass(llvm::SPIRV::StorageClass SC);
SPIRV::MemorySemantics::MemorySemantics
getMemSemanticsForStorageClass(SPIRV::StorageClass::StorageClass SC);
llvm::SPIRV::MemorySemantics getMemSemantics(llvm::AtomicOrdering Ord);
SPIRV::MemorySemantics::MemorySemantics getMemSemantics(AtomicOrdering Ord);
// Find def instruction for the given ConstReg, walking through
// spv_track_constant and ASSIGN_TYPE instructions. Updates ConstReg by def
// of OpConstant instruction.
llvm::MachineInstr *
getDefInstrMaybeConstant(llvm::Register &ConstReg,
const llvm::MachineRegisterInfo *MRI);
MachineInstr *getDefInstrMaybeConstant(Register &ConstReg,
const MachineRegisterInfo *MRI);
// Get constant integer value of the given ConstReg.
uint64_t getIConstVal(llvm::Register ConstReg,
const llvm::MachineRegisterInfo *MRI);
uint64_t getIConstVal(Register ConstReg, const MachineRegisterInfo *MRI);
// Check if MI is a SPIR-V specific intrinsic call.
bool isSpvIntrinsic(llvm::MachineInstr &MI, llvm::Intrinsic::ID IntrinsicID);
bool isSpvIntrinsic(MachineInstr &MI, Intrinsic::ID IntrinsicID);
// Get type of i-th operand of the metadata node.
llvm::Type *getMDOperandAsType(const llvm::MDNode *N, unsigned I);
Type *getMDOperandAsType(const MDNode *N, unsigned I);
} // namespace llvm
#endif // LLVM_LIB_TARGET_SPIRV_SPIRVUTILS_H