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Delete dead stores 

llvm-svn: 365903
This commit is contained in:
Fangrui Song 2019-07-12 14:58:15 +00:00
parent a196469e67
commit b251cc0d91
17 changed files with 27 additions and 58 deletions
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11
llvm/lib/Analysis/ScalarEvolution.cpp
View File

@ -10708,13 +10708,10 @@ ScalarEvolution::howManyGreaterThans(const SCEV *LHS, const SCEV *RHS,
IsSigned ? APIntOps::smax(getSignedRangeMin(RHS), Limit)
: APIntOps::umax(getUnsignedRangeMin(RHS), Limit);
const SCEV *MaxBECount = getCouldNotCompute();
if (isa<SCEVConstant>(BECount))
MaxBECount = BECount;
else
MaxBECount = computeBECount(getConstant(MaxStart - MinEnd),
getConstant(MinStride), false);
const SCEV *MaxBECount = isa<SCEVConstant>(BECount)
? BECount
: computeBECount(getConstant(MaxStart - MinEnd),
getConstant(MinStride), false);
if (isa<SCEVCouldNotCompute>(MaxBECount))
MaxBECount = BECount;

4
llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
View File

@ -1855,12 +1855,10 @@ LegalizerHelper::fewerElementsVectorMultiEltType(
LLT DstTy = MRI.getType(DstReg);
LLT LeftoverTy0;
int NumParts, NumLeftover;
// All of the operands need to have the same number of elements, so if we can
// determine a type breakdown for the result type, we can for all of the
// source types.
std::tie(NumParts, NumLeftover)
= getNarrowTypeBreakDown(DstTy, NarrowTy0, LeftoverTy0);
int NumParts = getNarrowTypeBreakDown(DstTy, NarrowTy0, LeftoverTy0).first;
if (NumParts < 0)
return UnableToLegalize;

4
llvm/lib/CodeGen/LiveDebugVariables.cpp
View File

@ -740,10 +740,8 @@ void UserValue::extendDef(SlotIndex Idx, DbgValueLocation Loc, LiveRange *LR,
}
// Limited by the next def.
if (I.valid() && I.start() < Stop) {
if (I.valid() && I.start() < Stop)
Stop = I.start();
ToEnd = false;
}
// Limited by VNI's live range.
else if (!ToEnd && Kills)
Kills->push_back(Stop);

4
llvm/lib/CodeGen/SafeStack.cpp
View File

@ -587,10 +587,6 @@ Value *SafeStack::moveStaticAllocasToUnsafeStack(
IRB.SetInsertPoint(AI);
unsigned Offset = SSL.getObjectOffset(AI);
uint64_t Size = getStaticAllocaAllocationSize(AI);
if (Size == 0)
Size = 1; // Don't create zero-sized stack objects.
replaceDbgDeclareForAlloca(AI, BasePointer, DIB, DIExpression::ApplyOffset,
-Offset);
replaceDbgValueForAlloca(AI, BasePointer, DIB, -Offset);

6
llvm/lib/CodeGen/TargetPassConfig.cpp
View File

@ -1046,12 +1046,8 @@ defaultRegAlloc("default",
useDefaultRegisterAllocator);
static void initializeDefaultRegisterAllocatorOnce() {
RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getDefault();
if (!Ctor) {
Ctor = RegAlloc;
if (!RegisterRegAlloc::getDefault())
RegisterRegAlloc::setDefault(RegAlloc);
}
}
/// Instantiate the default register allocator pass for this target for either

1
llvm/lib/MC/MCParser/AsmParser.cpp
View File

@ -3424,7 +3424,6 @@ bool AsmParser::parseDirectiveFile(SMLoc DirectiveLoc) {
FileNumber, Directory, Filename, CKMem, Source);
if (!FileNumOrErr)
return Error(DirectiveLoc, toString(FileNumOrErr.takeError()));
FileNumber = FileNumOrErr.get();
}
// Alert the user if there are some .file directives with MD5 and some not.
// But only do that once.

1
llvm/lib/MC/WasmObjectWriter.cpp
View File

@ -1413,7 +1413,6 @@ uint64_t WasmObjectWriter::writeObject(MCAssembler &Asm,
} else {
// An import; the index was assigned above.
assert(WasmIndices.count(&WS) > 0);
Index = WasmIndices.find(&WS)->second;
}
LLVM_DEBUG(dbgs() << " -> event index: " << WasmIndices.find(&WS)->second
<< "\n");

1
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
View File

@ -2753,7 +2753,6 @@ bool AMDGPUAsmParser::validateConstantBusLimitations(const MCInst &Inst) {
SGPRsUsed.insert(Reg);
++ConstantBusUseCount;
}
SGPRUsed = Reg;
} else { // Expression or a literal
if (Desc.OpInfo[OpIdx].OperandType == MCOI::OPERAND_IMMEDIATE)

13
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
View File

@ -5071,8 +5071,7 @@ void SIInstrInfo::lowerScalarXnor(SetVectorType &Worklist,
RI.isSGPRClass(MRI.getRegClass(Src0.getReg()));
bool Src1IsSGPR = Src1.isReg() &&
RI.isSGPRClass(MRI.getRegClass(Src1.getReg()));
MachineInstr *Not = nullptr;
MachineInstr *Xor = nullptr;
MachineInstr *Xor;
unsigned Temp = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
unsigned NewDest = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
@ -5080,14 +5079,12 @@ void SIInstrInfo::lowerScalarXnor(SetVectorType &Worklist,
// The next iteration over the work list will lower these to the vector
// unit as necessary.
if (Src0IsSGPR) {
Not = BuildMI(MBB, MII, DL, get(AMDGPU::S_NOT_B32), Temp)
.add(Src0);
BuildMI(MBB, MII, DL, get(AMDGPU::S_NOT_B32), Temp).add(Src0);
Xor = BuildMI(MBB, MII, DL, get(AMDGPU::S_XOR_B32), NewDest)
.addReg(Temp)
.add(Src1);
} else if (Src1IsSGPR) {
Not = BuildMI(MBB, MII, DL, get(AMDGPU::S_NOT_B32), Temp)
.add(Src1);
BuildMI(MBB, MII, DL, get(AMDGPU::S_NOT_B32), Temp).add(Src1);
Xor = BuildMI(MBB, MII, DL, get(AMDGPU::S_XOR_B32), NewDest)
.add(Src0)
.addReg(Temp);
@ -5095,8 +5092,8 @@ void SIInstrInfo::lowerScalarXnor(SetVectorType &Worklist,
Xor = BuildMI(MBB, MII, DL, get(AMDGPU::S_XOR_B32), Temp)
.add(Src0)
.add(Src1);
Not = BuildMI(MBB, MII, DL, get(AMDGPU::S_NOT_B32), NewDest)
.addReg(Temp);
MachineInstr *Not =
BuildMI(MBB, MII, DL, get(AMDGPU::S_NOT_B32), NewDest).addReg(Temp);
Worklist.insert(Not);
}

2
llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
View File

@ -145,7 +145,7 @@ private:
// only contains a single address space.
if ((OrderingAddrSpace == InstrAddrSpace) &&
isPowerOf2_32(uint32_t(InstrAddrSpace)))
IsCrossAddressSpaceOrdering = false;
this->IsCrossAddressSpaceOrdering = false;
}
public:

6
llvm/lib/Target/AVR/AVRRegisterInfo.cpp
View File

@ -233,9 +233,9 @@ void AVRRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
// No need to set SREG as dead here otherwise if the next instruction is a
// cond branch it will be using a dead register.
New = BuildMI(MBB, std::next(II), dl, TII.get(SubOpc), AVR::R29R28)
.addReg(AVR::R29R28, RegState::Kill)
.addImm(Offset - 63 + 1);
BuildMI(MBB, std::next(II), dl, TII.get(SubOpc), AVR::R29R28)
.addReg(AVR::R29R28, RegState::Kill)
.addImm(Offset - 63 + 1);
Offset = 62;
}

3
llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
View File

@ -185,7 +185,7 @@ encodeInstruction(const MCInst &MI, raw_ostream &OS,
// Check for unimplemented opcodes.
// Unfortunately in MIPS both NOP and SLL will come in with Binary == 0
// so we have to special check for them.
unsigned Opcode = TmpInst.getOpcode();
const unsigned Opcode = TmpInst.getOpcode();
if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) &&
(Opcode != Mips::SLL_MM) && (Opcode != Mips::SLL_MMR6) && !Binary)
llvm_unreachable("unimplemented opcode in encodeInstruction()");
@ -208,7 +208,6 @@ encodeInstruction(const MCInst &MI, raw_ostream &OS,
if (Fixups.size() > N)
Fixups.pop_back();
Opcode = NewOpcode;
TmpInst.setOpcode (NewOpcode);
Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
}

12
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
View File

@ -1772,7 +1772,6 @@ bool PPCInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
return false;
PPC::Predicate Pred = (PPC::Predicate)UseMI->getOperand(0).getImm();
PPC::Predicate NewPred = Pred;
unsigned PredCond = PPC::getPredicateCondition(Pred);
unsigned PredHint = PPC::getPredicateHint(Pred);
int16_t Immed = (int16_t)Value;
@ -1782,21 +1781,20 @@ bool PPCInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
if (Immed == -1 && PredCond == PPC::PRED_GT)
// We convert "greater than -1" into "greater than or equal to 0",
// since we are assuming signed comparison by !equalityOnly
NewPred = PPC::getPredicate(PPC::PRED_GE, PredHint);
Pred = PPC::getPredicate(PPC::PRED_GE, PredHint);
else if (Immed == -1 && PredCond == PPC::PRED_LE)
// We convert "less than or equal to -1" into "less than 0".
NewPred = PPC::getPredicate(PPC::PRED_LT, PredHint);
Pred = PPC::getPredicate(PPC::PRED_LT, PredHint);
else if (Immed == 1 && PredCond == PPC::PRED_LT)
// We convert "less than 1" into "less than or equal to 0".
NewPred = PPC::getPredicate(PPC::PRED_LE, PredHint);
Pred = PPC::getPredicate(PPC::PRED_LE, PredHint);
else if (Immed == 1 && PredCond == PPC::PRED_GE)
// We convert "greater than or equal to 1" into "greater than 0".
NewPred = PPC::getPredicate(PPC::PRED_GT, PredHint);
Pred = PPC::getPredicate(PPC::PRED_GT, PredHint);
else
return false;
PredsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(0)),
NewPred));
PredsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(0)), Pred));
}
// Search for Sub.

2
llvm/lib/Transforms/Scalar/InductiveRangeCheckElimination.cpp
View File

@ -859,7 +859,7 @@ LoopStructure::parseLoopStructure(ScalarEvolution &SE,
assert(!StepCI->isZero() && "Zero step?");
bool IsIncreasing = !StepCI->isNegative();
bool IsSignedPredicate = ICmpInst::isSigned(Pred);
bool IsSignedPredicate;
const SCEV *StartNext = IndVarBase->getStart();
const SCEV *Addend = SE.getNegativeSCEV(IndVarBase->getStepRecurrence(SE));
const SCEV *IndVarStart = SE.getAddExpr(StartNext, Addend);

4
llvm/lib/Transforms/Scalar/LoopInterchange.cpp
View File

@ -1264,9 +1264,7 @@ bool LoopInterchangeTransform::transform() {
}
void LoopInterchangeTransform::splitInnerLoopLatch(Instruction *Inc) {
BasicBlock *InnerLoopLatch = InnerLoop->getLoopLatch();
BasicBlock *InnerLoopLatchPred = InnerLoopLatch;
InnerLoopLatch = SplitBlock(InnerLoopLatchPred, Inc, DT, LI);
SplitBlock(InnerLoop->getLoopLatch(), Inc, DT, LI);
}
/// \brief Move all instructions except the terminator from FromBB right before

2
llvm/lib/Transforms/Utils/InlineFunction.cpp
View File

@ -1499,7 +1499,7 @@ void llvm::updateProfileCallee(
return;
uint64_t priorEntryCount = CalleeCount.getCount();
uint64_t newEntryCount = priorEntryCount;
uint64_t newEntryCount;
// Since CallSiteCount is an estimate, it could exceed the original callee
// count and has to be set to 0 so guard against underflow.

9
llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp
View File

@ -1152,13 +1152,8 @@ bool Vectorizer::vectorizeLoadChain(
vectorizeLoadChain(Chains.second, InstructionsProcessed);
}
unsigned NewAlign = getOrEnforceKnownAlignment(L0->getPointerOperand(),
StackAdjustedAlignment,
DL, L0, nullptr, &DT);
if (NewAlign != 0)
Alignment = NewAlign;
Alignment = NewAlign;
Alignment = getOrEnforceKnownAlignment(
L0->getPointerOperand(), StackAdjustedAlignment, DL, L0, nullptr, &DT);
}
if (!TTI.isLegalToVectorizeLoadChain(SzInBytes, Alignment, AS)) {