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retpoline insertion : further updates. 

Summary:
Couple of updates:

1) Handle address pattern with segment register.
2) Assume R11 available for PLT calls always.
3) Add CFI state to each BB.
4) early exit getMacroOpFusionPair if Instruction.size() <2.

(cherry picked from FBD9172426)
This commit is contained in:
Laith Saed Sakka 2018-08-03 16:36:06 -07:00 committed by Maksim Panchenko
parent c35dc2a386
commit b2382dc552
5 changed files with 35 additions and 19 deletions
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2
bolt/src/BinaryBasicBlock.cpp
View File

@ -358,7 +358,7 @@ BinaryBasicBlock::getMacroOpFusionPair() const {
if (!Function->getBinaryContext().isX86())
return end();
if (succ_size() != 2)
if (getNumNonPseudos() < 2 || succ_size() != 2)
return end();
auto RI = getLastNonPseudo();

9
bolt/src/MCPlusBuilder.h
View File

@ -1298,10 +1298,11 @@ public:
return false;
}
virtual bool createLoad(MCInst &Inst, const MCPhysReg &BaseReg, int Scale,
const MCPhysReg &IndexReg, int Offset,
const MCExpr *OffsetExpr, const MCPhysReg &DstReg,
int Size) const {
virtual bool createLoad(MCInst &Inst, const MCPhysReg &BaseReg, int64_t Scale,
const MCPhysReg &IndexReg, int64_t Offset,
const MCExpr *OffsetExpr,
const MCPhysReg &AddrSegmentReg,
const MCPhysReg &DstReg, int Size) const {
llvm_unreachable("not implemented");
return false;
}

1
bolt/src/Passes/PLTCall.cpp
View File

@ -76,6 +76,7 @@ void PLTCall::runOnFunctions(
BC.MIB->convertCallToIndirectCall(Instr,
CalleeBF->getPLTSymbol(),
BC.Ctx.get());
BC.MIB->addAnnotation(Instr, "PLTCall", true);
++NumCallsOptimized;
}
}

26
bolt/src/Passes/RetpolineInsertion.cpp
View File

@ -95,6 +95,7 @@ BinaryFunction *createNewRetpoline(BinaryContext &BC,
Ctx.createTempSymbol(Twine(RetpolineTag + "_BB" + to_string(I)), true);
NewBlocks[I] = NewRetpoline->createBasicBlock(
BinaryBasicBlock::INVALID_OFFSET, Symbol);
NewBlocks[I].get()->setCFIState(0);
}
auto &BB0 = *NewBlocks[0].get();
@ -139,7 +140,8 @@ BinaryFunction *createNewRetpoline(BinaryContext &BC,
MCInst LoadCalleeAddrs;
MIB.createLoad(LoadCalleeAddrs, BrInfo.BaseRegNum, BrInfo.ScaleValue,
BrInfo.IndexRegNum, BrInfo.DispValue, BrInfo.DispExpr,
MIB.getX86R11(), 8);
BrInfo.SegRegNum, MIB.getX86R11(), 8);
BB2.addInstruction(LoadCalleeAddrs);
MCInst StoreToStack;
@ -194,13 +196,19 @@ std::string createRetpolineFunctionTag(BinaryContext &BC,
Tag += BrInfo.BaseRegNum != BC.MIB->getX86NoRegister()
? "r" + to_string(BrInfo.BaseRegNum)
: "";
Tag += BrInfo.DispValue ? "+" + to_string(BrInfo.DispValue) : "";
Tag += BrInfo.DispExpr ? "+" + DispExprStr : "";
Tag +=
BrInfo.DispExpr ? "+" + DispExprStr : "+" + to_string(BrInfo.DispValue);
Tag += BrInfo.IndexRegNum != BC.MIB->getX86NoRegister()
? "+" + to_string(BrInfo.ScaleValue) + "*" +
to_string(BrInfo.IndexRegNum)
: "";
Tag += BrInfo.SegRegNum != BC.MIB->getX86NoRegister()
? "_seg_" + to_string(BrInfo.SegRegNum)
: "";
return Tag;
}
@ -227,7 +235,7 @@ void createBranchReplacement(BinaryContext &BC,
MCInst LoadCalleeAddrs;
MIB.createLoad(LoadCalleeAddrs, BrInfo.BaseRegNum, BrInfo.ScaleValue,
BrInfo.IndexRegNum, BrInfo.DispValue, BrInfo.DispExpr,
MIB.getX86R11(), 8);
BrInfo.SegRegNum, MIB.getX86R11(), 8);
Replacement.push_back(LoadCalleeAddrs);
}
@ -250,7 +258,7 @@ IndirectBranchInfo::IndirectBranchInfo(MCInst &Inst, MCPlusBuilder &MIB) {
if (!MIB.evaluateX86MemoryOperand(Inst, &BaseRegNum, &ScaleValue,
&IndexRegNum, &DispValue, &SegRegNum,
&DispExpr)) {
assert(false && "not expected");
llvm_unreachable("not expected");
}
} else if (MIB.isBranchOnReg(Inst)) {
assert(MCPlus::getNumPrimeOperands(Inst) == 1 && "expect 1 operand");
@ -290,7 +298,9 @@ void RetpolineInsertion::runOnFunctions(BinaryContext &BC,
// Determine if r11 is available before this instruction
if (BrInfo.isMem()) {
if (opts::R11Availability == AvailabilityOptions::ALWAYS)
if(MIB.hasAnnotation(Inst, "PLTCall"))
R11Available= true;
else if (opts::R11Availability == AvailabilityOptions::ALWAYS)
R11Available = true;
else if (opts::R11Availability == AvailabilityOptions::ABI)
R11Available = BrInfo.isCall();
@ -317,9 +327,9 @@ void RetpolineInsertion::runOnFunctions(BinaryContext &BC,
}
}
}
outs() << "The number of created retpoline functions is : "
outs() << "BOLT-INFO: The number of created retpoline functions is : "
<< CreatedRetpolines.size()
<< "\nThe number of retpolined branches is : " << RetpolinedBranches
<< "\nBOLT-INFO: The number of retpolined branches is : " << RetpolinedBranches
<< "\n";
}

16
bolt/src/Target/X86/X86MCPlusBuilder.cpp
View File

@ -1040,6 +1040,9 @@ public:
} else {
assert(DispExpr && "DispExpr needs to be set");
*DispExpr = Disp.getExpr();
if (DispImm) {
*DispImm = 0;
}
}
*SegmentRegNum = Segment.getReg();
return true;
@ -2667,13 +2670,14 @@ public:
int Offset, const MCPhysReg &DstReg,
int Size) const override {
return createLoad(Inst, StackReg, /*Scale=*/1, /*IndexReg=*/X86::NoRegister,
Offset, nullptr, DstReg, Size);
Offset, nullptr, /*AddrSegmentReg=*/X86::NoRegister,
DstReg, Size);
}
bool createLoad(MCInst &Inst, const MCPhysReg &BaseReg, int Scale,
const MCPhysReg &IndexReg, int Offset,
const MCExpr *OffsetExpr, const MCPhysReg &DstReg,
int Size) const{
bool createLoad(MCInst &Inst, const MCPhysReg &BaseReg, int64_t Scale,
const MCPhysReg &IndexReg, int64_t Offset,
const MCExpr *OffsetExpr, const MCPhysReg &AddrSegmentReg,
const MCPhysReg &DstReg, int Size) const {
unsigned NewOpcode;
switch (Size) {
default:
@ -2692,7 +2696,7 @@ public:
Inst.addOperand(MCOperand::createExpr(OffsetExpr)); // Displacement
else
Inst.addOperand(MCOperand::createImm(Offset)); // Displacement
Inst.addOperand(MCOperand::createReg(X86::NoRegister)); // AddrSegmentReg
Inst.addOperand(MCOperand::createReg(AddrSegmentReg)); // AddrSegmentReg
return true;
}