forked from OSchip/llvm-project
Convert over DForm and DSForm instructions
llvm-svn: 21348
This commit is contained in:
Chris Lattner
parent
15709c2c33
commit
b2367e398e
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@ -90,8 +90,8 @@ class BForm_ext<bits<6> opcode, bit aa, bit lk, bits<5> bo, bits<2> bicode,
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}
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// 1.7.4 D-Form
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class DForm_base<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
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: I<opcode, ppc64, vmx, OL, asmstr> {
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class DForm_base<bits<6> opcode, dag OL, string asmstr>
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: I<opcode, 0, 0, OL, asmstr> {
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bits<5> A;
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bits<5> B;
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bits<16> C;
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@ -101,8 +101,8 @@ class DForm_base<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
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let Inst{16-31} = C;
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}
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class DForm_1<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
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: I<opcode, ppc64, vmx, OL, asmstr> {
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class DForm_1<bits<6> opcode, dag OL, string asmstr>
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: I<opcode, 0, 0, OL, asmstr> {
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bits<5> A;
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bits<16> C;
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bits<5> B;
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@ -112,11 +112,11 @@ class DForm_1<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
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let Inst{16-31} = C;
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}
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class DForm_2<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
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: DForm_base<opcode, ppc64, vmx, OL, asmstr>;
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class DForm_2<bits<6> opcode, dag OL, string asmstr>
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: DForm_base<opcode, OL, asmstr>;
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class DForm_2_r0<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
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: I<opcode, ppc64, vmx, OL, asmstr> {
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class DForm_2_r0<bits<6> opcode, dag OL, string asmstr>
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: I<opcode, 0, 0, OL, asmstr> {
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bits<5> A;
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bits<16> B;
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@ -126,11 +126,11 @@ class DForm_2_r0<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
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}
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// Currently we make the use/def reg distinction in ISel, not tablegen
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class DForm_3<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
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: DForm_1<opcode, ppc64, vmx, OL, asmstr>;
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class DForm_3<bits<6> opcode, dag OL, string asmstr>
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: DForm_1<opcode, OL, asmstr>;
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class DForm_4<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
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: I<opcode, ppc64, vmx, OL, asmstr> {
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class DForm_4<bits<6> opcode, dag OL, string asmstr>
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: I<opcode, 0, 0, OL, asmstr> {
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bits<5> B;
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bits<5> A;
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bits<16> C;
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@ -140,15 +140,15 @@ class DForm_4<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
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let Inst{16-31} = C;
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}
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class DForm_4_zero<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
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: DForm_1<opcode, ppc64, vmx, OL, asmstr> {
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class DForm_4_zero<bits<6> opcode, dag OL, string asmstr>
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: DForm_1<opcode, OL, asmstr> {
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let A = 0;
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let B = 0;
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let C = 0;
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}
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class DForm_5<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
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: I<opcode, ppc64, vmx, OL, asmstr> {
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class DForm_5<bits<6> opcode, dag OL, string asmstr>
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: I<opcode, 0, 0, OL, asmstr> {
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bits<3> BF;
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bits<1> L;
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bits<5> RA;
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@ -161,30 +161,30 @@ class DForm_5<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
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let Inst{16-31} = I;
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}
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class DForm_5_ext<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
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: DForm_5<opcode, ppc64, vmx, OL, asmstr> {
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let L = ppc64;
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class DForm_5_ext<bits<6> opcode, dag OL, string asmstr>
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: DForm_5<opcode, OL, asmstr> {
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let L = PPC64;
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}
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class DForm_6<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
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: DForm_5<opcode, ppc64, vmx, OL, asmstr>;
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class DForm_6<bits<6> opcode, dag OL, string asmstr>
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: DForm_5<opcode, OL, asmstr>;
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class DForm_6_ext<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
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: DForm_6<opcode, ppc64, vmx, OL, asmstr> {
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let L = ppc64;
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class DForm_6_ext<bits<6> opcode, dag OL, string asmstr>
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: DForm_6<opcode, OL, asmstr> {
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let L = PPC64;
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}
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class DForm_8<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
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: DForm_1<opcode, ppc64, vmx, OL, asmstr> {
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class DForm_8<bits<6> opcode, dag OL, string asmstr>
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: DForm_1<opcode, OL, asmstr> {
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}
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class DForm_9<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
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: DForm_1<opcode, ppc64, vmx, OL, asmstr> {
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class DForm_9<bits<6> opcode, dag OL, string asmstr>
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: DForm_1<opcode, OL, asmstr> {
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}
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// 1.7.5 DS-Form
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class DSForm_1<bits<6> opcode, bits<2> xo, bit ppc64, bit vmx,
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dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
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class DSForm_1<bits<6> opcode, bits<2> xo, dag OL, string asmstr>
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: I<opcode, 0, 0, OL, asmstr> {
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bits<5> RST;
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bits<14> DS;
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bits<5> RA;
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@ -195,9 +195,8 @@ class DSForm_1<bits<6> opcode, bits<2> xo, bit ppc64, bit vmx,
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let Inst{30-31} = xo;
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}
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class DSForm_2<bits<6> opcode, bits<2> xo, bit ppc64, bit vmx,
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dag OL, string asmstr>
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: DSForm_1<opcode, xo, ppc64, vmx, OL, asmstr>;
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class DSForm_2<bits<6> opcode, bits<2> xo, dag OL, string asmstr>
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: DSForm_1<opcode, xo, OL, asmstr>;
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// 1.7.6 X-Form
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class XForm_base_r3xo<bits<6> opcode, bits<10> xo, bit rc,
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@ -101,113 +101,104 @@ let isBranch = 1, isTerminator = 1, isCall = 1,
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// register and an immediate are of this type.
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//
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let isLoad = 1 in {
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def LBZ : DForm_1<34, 0, 0, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
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def LBZ : DForm_1<34, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
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"lbz $rD, $disp($rA)">;
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def LHA : DForm_1<42, 0, 0, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
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def LHA : DForm_1<42, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
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"lha $rD, $disp($rA)">;
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def LHZ : DForm_1<40, 0, 0, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
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def LHZ : DForm_1<40, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
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"lhz $rD, $disp($rA)">;
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def LMW : DForm_1<46, 0, 0, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
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def LMW : DForm_1<46, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
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"lmw $rD, $disp($rA)">;
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def LWZ : DForm_1<32, 0, 0, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
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def LWZ : DForm_1<32, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
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"lwz $rD, $disp($rA)">;
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def LWZU : DForm_1<35, 0, 0, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
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def LWZU : DForm_1<35, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
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"lwzu $rD, $disp($rA)">;
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}
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def ADDI : DForm_2<14, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
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def ADDI : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
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"addi $rD, $rA, $imm">;
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def ADDIC : DForm_2<12, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
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def ADDIC : DForm_2<12, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
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"addic $rD, $rA, $imm">;
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def ADDICo : DForm_2<13, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
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def ADDICo : DForm_2<13, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
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"addic. $rD, $rA, $imm">;
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def ADDIS : DForm_2<15, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
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def ADDIS : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
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"addis $rD, $rA, $imm">;
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def LA : DForm_2<14, 0, 0, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym),
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def LA : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym),
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"la $rD, $sym($rA)">;
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def LOADHiAddr : DForm_2<15, 0, 0, (ops GPRC:$rD, GPRC:$rA, symbolHi:$sym),
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def LOADHiAddr : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, symbolHi:$sym),
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"addis $rD, $rA, $sym">;
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def MULLI : DForm_2< 7, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
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def MULLI : DForm_2< 7, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
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"mulli $rD, $rA, $imm">;
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def SUBFIC : DForm_2< 8, 0, 0, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
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def SUBFIC : DForm_2< 8, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
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"subfic $rD, $rA, $imm">;
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def LI : DForm_2_r0<14, 0, 0, (ops GPRC:$rD, s16imm:$imm),
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def LI : DForm_2_r0<14, (ops GPRC:$rD, s16imm:$imm),
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"li $rD, $imm">;
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def LIS : DForm_2_r0<15, 0, 0, (ops GPRC:$rD, s16imm:$imm),
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def LIS : DForm_2_r0<15, (ops GPRC:$rD, s16imm:$imm),
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"lis $rD, $imm">;
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let isStore = 1 in {
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def STMW : DForm_3<47, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
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def STMW : DForm_3<47, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
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"stmw $rS, $disp($rA)">;
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def STB : DForm_3<38, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
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def STB : DForm_3<38, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
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"stb $rS, $disp($rA)">;
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def STH : DForm_3<44, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
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def STH : DForm_3<44, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
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"sth $rS, $disp($rA)">;
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def STW : DForm_3<36, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
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def STW : DForm_3<36, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
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"stw $rS, $disp($rA)">;
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def STWU : DForm_3<37, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
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def STWU : DForm_3<37, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
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"stwu $rS, $disp($rA)">;
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}
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let Defs = [CR0] in {
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def ANDIo : DForm_4<28, 0, 0,
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(ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
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def ANDIo : DForm_4<28, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
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"andi. $dst, $src1, $src2">;
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def ANDISo : DForm_4<29, 0, 0,
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(ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
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def ANDISo : DForm_4<29, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
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"andis. $dst, $src1, $src2">;
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}
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def ORI : DForm_4<24, 0, 0,
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(ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
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def ORI : DForm_4<24, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
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"ori $dst, $src1, $src2">;
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def ORIS : DForm_4<25, 0, 0,
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(ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
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def ORIS : DForm_4<25, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
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"oris $dst, $src1, $src2">;
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def XORI : DForm_4<26, 0, 0,
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(ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
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def XORI : DForm_4<26, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
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"xori $dst, $src1, $src2">;
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def XORIS : DForm_4<27, 0, 0,
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(ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
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def XORIS : DForm_4<27, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
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"xoris $dst, $src1, $src2">;
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def NOP : DForm_4_zero<24, 0, 0, (ops), "nop">;
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def CMPI : DForm_5<11, 0, 0, (ops CRRC:$crD, i1imm:$L, GPRC:$rA, s16imm:$imm),
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def NOP : DForm_4_zero<24, (ops), "nop">;
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def CMPI : DForm_5<11, (ops CRRC:$crD, i1imm:$L, GPRC:$rA, s16imm:$imm),
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"cmpi $crD, $L, $rA, $imm">;
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def CMPWI : DForm_5_ext<11, 0, 0, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
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def CMPWI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
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"cmpwi $crD, $rA, $imm">;
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def CMPDI : DForm_5_ext<11, 1, 0, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
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"cmpdi $crD, $rA, $imm">;
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def CMPLI : DForm_6<10, 0, 0,
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(ops CRRC:$dst, i1imm:$size, GPRC:$src1, u16imm:$src2),
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def CMPDI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
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"cmpdi $crD, $rA, $imm">, isPPC64;
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def CMPLI : DForm_6<10, (ops CRRC:$dst, i1imm:$size, GPRC:$src1, u16imm:$src2),
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"cmpli $dst, $size, $src1, $src2">;
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def CMPLWI : DForm_6_ext<10, 0, 0,
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(ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
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def CMPLWI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
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"cmplwi $dst, $src1, $src2">;
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def CMPLDI : DForm_6_ext<10, 1, 0,
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(ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
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"cmpldi $dst, $src1, $src2">;
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def CMPLDI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
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"cmpldi $dst, $src1, $src2">, isPPC64;
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let isLoad = 1 in {
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def LFS : DForm_8<48, 0, 0, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
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def LFS : DForm_8<48, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
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"lfs $rD, $disp($rA)">;
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def LFD : DForm_8<50, 0, 0, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
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def LFD : DForm_8<50, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
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"lfd $rD, $disp($rA)">;
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}
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let isStore = 1 in {
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def STFS : DForm_9<52, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
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def STFS : DForm_9<52, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
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"stfs $rS, $disp($rA)">;
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def STFD : DForm_9<54, 0, 0, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
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def STFD : DForm_9<54, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
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"stfd $rS, $disp($rA)">;
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}
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// DS-Form instructions. Load/Store instructions available in PPC-64
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//
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let isLoad = 1 in {
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def LWA : DSForm_1<58, 2, 1, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
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"lwa $rT, $DS($rA)">;
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def LD : DSForm_2<58, 0, 1, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
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"ld $rT, $DS($rA)">;
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def LWA : DSForm_1<58, 2, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
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"lwa $rT, $DS($rA)">, isPPC64;
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def LD : DSForm_2<58, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
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"ld $rT, $DS($rA)">, isPPC64;
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}
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let isStore = 1 in {
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def STD : DSForm_2<62, 0, 1, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
|
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"std $rT, $DS($rA)">;
|
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def STDU : DSForm_2<62, 1, 1, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
|
||||
"stdu $rT, $DS($rA)">;
|
||||
def STD : DSForm_2<62, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
|
||||
"std $rT, $DS($rA)">, isPPC64;
|
||||
def STDU : DSForm_2<62, 1, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
|
||||
"stdu $rT, $DS($rA)">, isPPC64;
|
||||
}
|
||||
|
||||
// X-Form instructions. Most instructions that perform an operation on a
|
||||
|
|
|
|||
Loading…
Reference in New Issue