From b2226e21c3619da10bb0bb9da6ae42eca816a7aa Mon Sep 17 00:00:00 2001
From: Dan Gohman <gohman@apple.com>
Date: Wed, 13 Aug 2008 20:19:35 +0000
Subject: [PATCH] Initial checkin of the new "fast" instruction selection
support. See the comments in FastISelEmitter.cpp for details on what this is.
This is currently experimental and unusable.
llvm-svn: 54751
---
llvm/Makefile.rules | 7 +-
llvm/include/llvm/CodeGen/FastISel.h | 71 ++++
llvm/lib/CodeGen/SelectionDAG/FastISel.cpp | 104 ++++++
llvm/utils/TableGen/FastISelEmitter.cpp | 362 +++++++++++++++++++++
llvm/utils/TableGen/FastISelEmitter.h | 38 +++
llvm/utils/TableGen/TableGen.cpp | 7 +
6 files changed, 588 insertions(+), 1 deletion(-)
create mode 100644 llvm/include/llvm/CodeGen/FastISel.h
create mode 100644 llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
create mode 100644 llvm/utils/TableGen/FastISelEmitter.cpp
create mode 100644 llvm/utils/TableGen/FastISelEmitter.h
diff --git a/llvm/Makefile.rules b/llvm/Makefile.rules
index b8006a2a1f74..a7a487991099 100644
--- a/llvm/Makefile.rules
+++ b/llvm/Makefile.rules
@@ -1296,9 +1296,14 @@ $(ObjDir)/%GenCodeEmitter.inc.tmp: %.td $(ObjDir)/.dir
$(TARGET:%=$(ObjDir)/%GenDAGISel.inc.tmp): \
$(ObjDir)/%GenDAGISel.inc.tmp : %.td $(ObjDir)/.dir
- $(Echo) "Building $(<F) instruction selector implementation with tblgen"
+ $(Echo) "Building $(<F) DAG instruction selector implementation with tblgen"
$(Verb) $(TableGen) -gen-dag-isel -o $(call SYSPATH, $@) $<
+$(TARGET:%=$(ObjDir)/%GenFastISel.inc.tmp): \
+$(ObjDir)/%GenFastISel.inc.tmp : %.td $(ObjDir)/.dir
+ $(Echo) "Building $(<F) \"fast\" instruction selector implementation with tblgen"
+ $(Verb) $(TableGen) -gen-fast-isel -o $(call SYSPATH, $@) $<
+
$(TARGET:%=$(ObjDir)/%GenSubtarget.inc.tmp): \
$(ObjDir)/%GenSubtarget.inc.tmp : %.td $(ObjDir)/.dir
$(Echo) "Building $(<F) subtarget information with tblgen"
diff --git a/llvm/include/llvm/CodeGen/FastISel.h b/llvm/include/llvm/CodeGen/FastISel.h
new file mode 100644
index 000000000000..ee0e120327b4
--- /dev/null
+++ b/llvm/include/llvm/CodeGen/FastISel.h
@@ -0,0 +1,71 @@
+//===-- FastISel.h - Definition of the FastISel class ---------------------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the FastISel class.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_CODEGEN_FASTISEL_H
+#define LLVM_CODEGEN_FASTISEL_H
+
+#include "llvm/BasicBlock.h"
+#include "llvm/ADT/DenseMap.h"
+#include "llvm/CodeGen/SelectionDAGNodes.h"
+
+namespace llvm {
+
+class MachineBasicBlock;
+class MachineFunction;
+class TargetInstrInfo;
+class TargetRegisterClass;
+
+/// This file defines the FastISel class. This is a fast-path instruction
+/// selection class that generates poor code and doesn't support illegal
+/// types or non-trivial lowering, but runs quickly.
+class FastISel {
+ MachineBasicBlock *MBB;
+ MachineFunction *MF;
+ const TargetInstrInfo *TII;
+
+public:
+ FastISel(MachineBasicBlock *mbb, MachineFunction *mf,
+ const TargetInstrInfo *tii)
+ : MBB(mbb), MF(mf), TII(tii) {}
+
+ /// SelectInstructions - Do "fast" instruction selection over the
+ /// LLVM IR instructions in the range [Begin, N) where N is either
+ /// End or the first unsupported instruction. Return N.
+ /// ValueMap is filled in with a mapping of LLVM IR Values to
+ /// register numbers.
+ BasicBlock::iterator
+ SelectInstructions(BasicBlock::iterator Begin, BasicBlock::iterator End,
+ DenseMap<const Value*, unsigned> &ValueMap);
+
+protected:
+ virtual unsigned FastEmit_(MVT::SimpleValueType VT,
+ ISD::NodeType Opcode);
+ virtual unsigned FastEmit_r(MVT::SimpleValueType VT,
+ ISD::NodeType Opcode, unsigned Op0);
+ virtual unsigned FastEmit_rr(MVT::SimpleValueType VT,
+ ISD::NodeType Opcode,
+ unsigned Op0, unsigned Op1);
+
+ unsigned FastEmitInst_(unsigned MachineInstOpcode,
+ const TargetRegisterClass *RC);
+ unsigned FastEmitInst_r(unsigned MachineInstOpcode,
+ const TargetRegisterClass *RC,
+ unsigned Op0);
+ unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
+ const TargetRegisterClass *RC,
+ unsigned Op0, unsigned Op1);
+};
+
+}
+
+#endif
diff --git a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
new file mode 100644
index 000000000000..6fe941fecbf5
--- /dev/null
+++ b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
@@ -0,0 +1,104 @@
+///===-- FastISel.cpp - Implementation of the FastISel class --------------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains the implementation of the FastISel class.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/CodeGen/FastISel.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/Target/TargetInstrInfo.h"
+using namespace llvm;
+
+BasicBlock::iterator
+FastISel::SelectInstructions(BasicBlock::iterator Begin, BasicBlock::iterator End,
+ DenseMap<const Value*, unsigned> &ValueMap) {
+ BasicBlock::iterator I = Begin;
+
+ for (; I != End; ++I) {
+ switch (I->getOpcode()) {
+ case Instruction::Add: {
+ unsigned Op0 = ValueMap[I->getOperand(0)];
+ unsigned Op1 = ValueMap[I->getOperand(1)];
+ MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true);
+ if (VT == MVT::Other || !VT.isSimple()) {
+ // Unhandled type. Halt "fast" selection and bail.
+ return I;
+ }
+ unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), ISD::ADD, Op0, Op1);
+ ValueMap[I] = ResultReg;
+ break;
+ }
+ default:
+ // Unhandled instruction. Halt "fast" selection and bail.
+ return I;
+ }
+ }
+
+ return I;
+}
+
+unsigned FastISel::FastEmit_(MVT::SimpleValueType, ISD::NodeType) {
+ return 0;
+}
+
+unsigned FastISel::FastEmit_r(MVT::SimpleValueType, ISD::NodeType,
+ unsigned /*Op0*/) {
+ return 0;
+}
+
+unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, ISD::NodeType,
+ unsigned /*Op0*/, unsigned /*Op0*/) {
+ return 0;
+}
+
+unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
+ const TargetRegisterClass* RC) {
+ MachineRegisterInfo &MRI = MF->getRegInfo();
+ const TargetInstrDesc &II = TII->get(MachineInstOpcode);
+ MachineInstr *MI = BuildMI(*MF, II);
+ unsigned ResultReg = MRI.createVirtualRegister(RC);
+
+ MI->addOperand(MachineOperand::CreateReg(ResultReg, true));
+
+ MBB->push_back(MI);
+ return ResultReg;
+}
+
+unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
+ const TargetRegisterClass *RC,
+ unsigned Op0) {
+ MachineRegisterInfo &MRI = MF->getRegInfo();
+ const TargetInstrDesc &II = TII->get(MachineInstOpcode);
+ MachineInstr *MI = BuildMI(*MF, II);
+ unsigned ResultReg = MRI.createVirtualRegister(RC);
+
+ MI->addOperand(MachineOperand::CreateReg(ResultReg, true));
+ MI->addOperand(MachineOperand::CreateReg(Op0, false));
+
+ MBB->push_back(MI);
+ return ResultReg;
+}
+
+unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
+ const TargetRegisterClass *RC,
+ unsigned Op0, unsigned Op1) {
+ MachineRegisterInfo &MRI = MF->getRegInfo();
+ const TargetInstrDesc &II = TII->get(MachineInstOpcode);
+ MachineInstr *MI = BuildMI(*MF, II);
+ unsigned ResultReg = MRI.createVirtualRegister(RC);
+
+ MI->addOperand(MachineOperand::CreateReg(ResultReg, true));
+ MI->addOperand(MachineOperand::CreateReg(Op0, false));
+ MI->addOperand(MachineOperand::CreateReg(Op1, false));
+
+ MBB->push_back(MI);
+ return ResultReg;
+}
diff --git a/llvm/utils/TableGen/FastISelEmitter.cpp b/llvm/utils/TableGen/FastISelEmitter.cpp
new file mode 100644
index 000000000000..8007b7ed702b
--- /dev/null
+++ b/llvm/utils/TableGen/FastISelEmitter.cpp
@@ -0,0 +1,362 @@
+//===- FastISelEmitter.cpp - Generate an instruction selector -------------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This tablegen backend emits a "fast" instruction selector.
+//
+// This instruction selection method is designed to emit very poor code
+// quickly. Also, it is not designed to do much lowering, so most illegal
+// types (e.g. i64 on 32-bit targets) and operations (e.g. calls) are not
+// supported and cannot easily be added. Blocks containing operations
+// that are not supported need to be handled by a more capable selector,
+// such as the SelectionDAG selector.
+//
+// The intended use for "fast" instruction selection is "-O0" mode
+// compilation, where the quality of the generated code is irrelevant when
+// weighed against the speed at which the code can be generated.
+//
+// If compile time is so important, you might wonder why we don't just
+// skip codegen all-together, emit LLVM bytecode files, and execute them
+// with an interpreter. The answer is that it would complicate linking and
+// debugging, and also because that isn't how a compiler is expected to
+// work in some circles.
+//
+// If you need better generated code or more lowering than what this
+// instruction selector provides, use the SelectionDAG (DAGISel) instruction
+// selector instead. If you're looking here because SelectionDAG isn't fast
+// enough, consider looking into improving the SelectionDAG infastructure
+// instead. At the time of this writing there remain several major
+// opportunities for improvement.
+//
+//===----------------------------------------------------------------------===//
+
+#include "FastISelEmitter.h"
+#include "Record.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/Streams.h"
+#include "llvm/ADT/VectorExtras.h"
+using namespace llvm;
+
+namespace {
+
+struct OperandsSignature {
+ std::vector<std::string> Operands;
+
+ bool operator<(const OperandsSignature &O) const {
+ return Operands < O.Operands;
+ }
+
+ bool empty() const { return Operands.empty(); }
+
+ void PrintParameters(std::ostream &OS) const {
+ for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
+ if (Operands[i] == "r") {
+ OS << "unsigned Op" << i;
+ } else {
+ assert("Unknown operand kind!");
+ abort();
+ }
+ if (i + 1 != e)
+ OS << ", ";
+ }
+ }
+
+ void PrintArguments(std::ostream &OS) const {
+ for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
+ if (Operands[i] == "r") {
+ OS << "Op" << i;
+ } else {
+ assert("Unknown operand kind!");
+ abort();
+ }
+ if (i + 1 != e)
+ OS << ", ";
+ }
+ }
+
+ void PrintManglingSuffix(std::ostream &OS) const {
+ for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
+ OS << Operands[i];
+ }
+ }
+};
+
+struct InstructionMemo {
+ std::string Name;
+ const CodeGenRegisterClass *RC;
+};
+
+}
+
+static std::string getOpcodeName(Record *Op, CodeGenDAGPatterns &CGP) {
+ return CGP.getSDNodeInfo(Op).getEnumName();
+}
+
+static std::string getLegalCName(std::string OpName) {
+ std::string::size_type pos = OpName.find("::");
+ if (pos != std::string::npos)
+ OpName.replace(pos, 2, "_");
+ return OpName;
+}
+
+void FastISelEmitter::run(std::ostream &OS) {
+ EmitSourceFileHeader("\"Fast\" Instruction Selector for the " +
+ CGP.getTargetInfo().getName() + " target", OS);
+
+ const CodeGenTarget &Target = CGP.getTargetInfo();
+
+ // Get the namespace to insert instructions into. Make sure not to pick up
+ // "TargetInstrInfo" by accidentally getting the namespace off the PHI
+ // instruction or something.
+ std::string InstNS;
+ for (CodeGenTarget::inst_iterator i = Target.inst_begin(),
+ e = Target.inst_end(); i != e; ++i) {
+ InstNS = i->second.Namespace;
+ if (InstNS != "TargetInstrInfo")
+ break;
+ }
+
+ OS << "namespace llvm {\n";
+ OS << "namespace " << InstNS << " {\n";
+ OS << "class FastISel;\n";
+ OS << "}\n";
+ OS << "}\n";
+ OS << "\n";
+
+ if (!InstNS.empty()) InstNS += "::";
+
+ typedef std::map<MVT::SimpleValueType, InstructionMemo> TypeMap;
+ typedef std::map<std::string, TypeMap> OpcodeTypeMap;
+ typedef std::map<OperandsSignature, OpcodeTypeMap> OperandsOpcodeTypeMap;
+ OperandsOpcodeTypeMap SimplePatterns;
+
+ // Create the supported type signatures.
+ OperandsSignature KnownOperands;
+ SimplePatterns[KnownOperands] = OpcodeTypeMap();
+ KnownOperands.Operands.push_back("r");
+ SimplePatterns[KnownOperands] = OpcodeTypeMap();
+ KnownOperands.Operands.push_back("r");
+ SimplePatterns[KnownOperands] = OpcodeTypeMap();
+
+ for (CodeGenDAGPatterns::ptm_iterator I = CGP.ptm_begin(),
+ E = CGP.ptm_end(); I != E; ++I) {
+ const PatternToMatch &Pattern = *I;
+
+ // For now, just look at Instructions, so that we don't have to worry
+ // about emitting multiple instructions for a pattern.
+ TreePatternNode *Dst = Pattern.getDstPattern();
+ if (Dst->isLeaf()) continue;
+ Record *Op = Dst->getOperator();
+ if (!Op->isSubClassOf("Instruction"))
+ continue;
+ CodeGenInstruction &II = CGP.getTargetInfo().getInstruction(Op->getName());
+ if (II.OperandList.empty())
+ continue;
+ Record *Op0Rec = II.OperandList[0].Rec;
+ if (!Op0Rec->isSubClassOf("RegisterClass"))
+ continue;
+ const CodeGenRegisterClass *DstRC = &Target.getRegisterClass(Op0Rec);
+ if (!DstRC)
+ continue;
+
+ // Inspect the pattern.
+ TreePatternNode *InstPatNode = Pattern.getSrcPattern();
+ if (!InstPatNode) continue;
+ if (InstPatNode->isLeaf()) continue;
+
+ Record *InstPatOp = InstPatNode->getOperator();
+ std::string OpcodeName = getOpcodeName(InstPatOp, CGP);
+ MVT::SimpleValueType VT = InstPatNode->getTypeNum(0);
+
+ // For now, filter out instructions which just set a register to
+ // an Operand, like MOV32ri.
+ if (InstPatOp->isSubClassOf("Operand"))
+ continue;
+
+ // Check all the operands. For now only accept register operands.
+ OperandsSignature Operands;
+ for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) {
+ TreePatternNode *Op = InstPatNode->getChild(i);
+ if (!Op->isLeaf())
+ goto continue_label;
+ DefInit *OpDI = dynamic_cast<DefInit*>(Op->getLeafValue());
+ if (!OpDI)
+ goto continue_label;
+ Record *OpLeafRec = OpDI->getDef();
+ if (!OpLeafRec->isSubClassOf("RegisterClass"))
+ goto continue_label;
+ const CodeGenRegisterClass *RC = &Target.getRegisterClass(OpLeafRec);
+ if (!RC)
+ goto continue_label;
+ if (Op->getTypeNum(0) != VT)
+ goto continue_label;
+ Operands.Operands.push_back("r");
+ }
+
+ // If it's not a known signature, ignore it.
+ if (!SimplePatterns.count(Operands))
+ continue;
+
+ // Ok, we found a pattern that we can handle. Remember it.
+ {
+ InstructionMemo Memo = { Pattern.getDstPattern()->getOperator()->getName(),
+ DstRC };
+ SimplePatterns[Operands][OpcodeName][VT] = Memo;
+ }
+
+ continue_label:;
+ }
+
+ OS << "#include \"llvm/CodeGen/FastISel.h\"\n";
+ OS << "\n";
+ OS << "namespace llvm {\n";
+ OS << "\n";
+
+ // Declare the target FastISel class.
+ OS << "class " << InstNS << "FastISel : public llvm::FastISel {\n";
+ for (OperandsOpcodeTypeMap::const_iterator OI = SimplePatterns.begin(),
+ OE = SimplePatterns.end(); OI != OE; ++OI) {
+ const OperandsSignature &Operands = OI->first;
+ const OpcodeTypeMap &OTM = OI->second;
+
+ for (OpcodeTypeMap::const_iterator I = OTM.begin(), E = OTM.end();
+ I != E; ++I) {
+ const std::string &Opcode = I->first;
+ const TypeMap &TM = I->second;
+
+ for (TypeMap::const_iterator TI = TM.begin(), TE = TM.end();
+ TI != TE; ++TI) {
+ MVT::SimpleValueType VT = TI->first;
+
+ OS << " unsigned FastEmit_" << getLegalCName(Opcode)
+ << "_" << getLegalCName(getName(VT)) << "(";
+ Operands.PrintParameters(OS);
+ OS << ");\n";
+ }
+
+ OS << " unsigned FastEmit_" << getLegalCName(Opcode)
+ << "(MVT::SimpleValueType VT";
+ if (!Operands.empty())
+ OS << ", ";
+ Operands.PrintParameters(OS);
+ OS << ");\n";
+ }
+
+ OS << "unsigned FastEmit_";
+ Operands.PrintManglingSuffix(OS);
+ OS << "(MVT::SimpleValueType VT, ISD::NodeType Opcode";
+ if (!Operands.empty())
+ OS << ", ";
+ Operands.PrintParameters(OS);
+ OS << ");\n";
+ }
+ OS << "public:\n";
+ OS << " FastISel(MachineBasicBlock *mbb, MachineFunction *mf, ";
+ OS << "const TargetInstrInfo *tii) : llvm::FastISel(mbb, mf, tii) {}\n";
+ OS << "};\n";
+ OS << "\n";
+
+ // Define the target FastISel creation function.
+ OS << "llvm::FastISel *" << InstNS
+ << "createFastISel(MachineBasicBlock *mbb, MachineFunction *mf, ";
+ OS << "const TargetInstrInfo *tii) {\n";
+ OS << " return new " << InstNS << "FastISel(mbb, mf, tii);\n";
+ OS << "}\n";
+ OS << "\n";
+
+ // Now emit code for all the patterns that we collected.
+ for (OperandsOpcodeTypeMap::const_iterator OI = SimplePatterns.begin(),
+ OE = SimplePatterns.end(); OI != OE; ++OI) {
+ const OperandsSignature &Operands = OI->first;
+ const OpcodeTypeMap &OTM = OI->second;
+
+ for (OpcodeTypeMap::const_iterator I = OTM.begin(), E = OTM.end();
+ I != E; ++I) {
+ const std::string &Opcode = I->first;
+ const TypeMap &TM = I->second;
+
+ OS << "// FastEmit functions for " << Opcode << ".\n";
+ OS << "\n";
+
+ // Emit one function for each opcode,type pair.
+ for (TypeMap::const_iterator TI = TM.begin(), TE = TM.end();
+ TI != TE; ++TI) {
+ MVT::SimpleValueType VT = TI->first;
+ const InstructionMemo &Memo = TI->second;
+
+ OS << "unsigned " << InstNS << "FastISel::FastEmit_"
+ << getLegalCName(Opcode)
+ << "_" << getLegalCName(getName(VT)) << "(";
+ Operands.PrintParameters(OS);
+ OS << ") {\n";
+ OS << " return FastEmitInst_";
+ Operands.PrintManglingSuffix(OS);
+ OS << "(" << InstNS << Memo.Name << ", ";
+ OS << InstNS << Memo.RC->getName() << "RegisterClass";
+ if (!Operands.empty())
+ OS << ", ";
+ Operands.PrintArguments(OS);
+ OS << ");\n";
+ OS << "}\n";
+ OS << "\n";
+ }
+
+ // Emit one function for the opcode that demultiplexes based on the type.
+ OS << "unsigned " << InstNS << "FastISel::FastEmit_"
+ << getLegalCName(Opcode) << "(MVT::SimpleValueType VT";
+ if (!Operands.empty())
+ OS << ", ";
+ Operands.PrintParameters(OS);
+ OS << ") {\n";
+ OS << " switch (VT) {\n";
+ for (TypeMap::const_iterator TI = TM.begin(), TE = TM.end();
+ TI != TE; ++TI) {
+ MVT::SimpleValueType VT = TI->first;
+ std::string TypeName = getName(VT);
+ OS << " case " << TypeName << ": return FastEmit_"
+ << getLegalCName(Opcode) << "_" << getLegalCName(TypeName) << "(";
+ Operands.PrintArguments(OS);
+ OS << ");\n";
+ }
+ OS << " default: return 0;\n";
+ OS << " }\n";
+ OS << "}\n";
+ OS << "\n";
+ }
+
+ // Emit one function for the operand signature that demultiplexes based
+ // on opcode and type.
+ OS << "unsigned " << InstNS << "FastISel::FastEmit_";
+ Operands.PrintManglingSuffix(OS);
+ OS << "(MVT::SimpleValueType VT, ISD::NodeType Opcode";
+ if (!Operands.empty())
+ OS << ", ";
+ Operands.PrintParameters(OS);
+ OS << ") {\n";
+ OS << " switch (Opcode) {\n";
+ for (OpcodeTypeMap::const_iterator I = OTM.begin(), E = OTM.end();
+ I != E; ++I) {
+ const std::string &Opcode = I->first;
+
+ OS << " case " << Opcode << ": return FastEmit_"
+ << getLegalCName(Opcode) << "(VT";
+ if (!Operands.empty())
+ OS << ", ";
+ Operands.PrintArguments(OS);
+ OS << ");\n";
+ }
+ OS << " default: return 0;\n";
+ OS << " }\n";
+ OS << "}\n";
+ OS << "\n";
+ }
+
+ OS << "}\n";
+}
+
+// todo: really filter out Constants
diff --git a/llvm/utils/TableGen/FastISelEmitter.h b/llvm/utils/TableGen/FastISelEmitter.h
new file mode 100644
index 000000000000..f34ece81b95e
--- /dev/null
+++ b/llvm/utils/TableGen/FastISelEmitter.h
@@ -0,0 +1,38 @@
+//===- FastISelEmitter.h - Generate an instruction selector -----*- C++ -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This tablegen backend emits a "fast" instruction selector.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef FASTISEL_EMITTER_H
+#define FASTISEL_EMITTER_H
+
+#include "TableGenBackend.h"
+#include "CodeGenDAGPatterns.h"
+#include <set>
+
+namespace llvm {
+
+/// FastISelEmitter - The top-level class which coordinates construction
+/// and emission of the instruction selector.
+///
+class FastISelEmitter : public TableGenBackend {
+ RecordKeeper &Records;
+ CodeGenDAGPatterns CGP;
+public:
+ explicit FastISelEmitter(RecordKeeper &R) : Records(R), CGP(R) {}
+
+ // run - Output the isel, returning true on failure.
+ void run(std::ostream &OS);
+};
+
+} // End llvm namespace
+
+#endif
diff --git a/llvm/utils/TableGen/TableGen.cpp b/llvm/utils/TableGen/TableGen.cpp
index 64b2f97dc306..d6e84609f430 100644
--- a/llvm/utils/TableGen/TableGen.cpp
+++ b/llvm/utils/TableGen/TableGen.cpp
@@ -29,6 +29,7 @@
#include "InstrEnumEmitter.h"
#include "AsmWriterEmitter.h"
#include "DAGISelEmitter.h"
+#include "FastISelEmitter.h"
#include "SubtargetEmitter.h"
#include "IntrinsicEmitter.h"
#include "LLVMCConfigurationEmitter.h"
@@ -45,6 +46,7 @@ enum ActionType {
GenInstrEnums, GenInstrs, GenAsmWriter,
GenCallingConv,
GenDAGISel,
+ GenFastISel,
GenSubtarget,
GenIntrinsic,
GenLLVMCConf,
@@ -74,6 +76,8 @@ namespace {
"Generate assembly writer"),
clEnumValN(GenDAGISel, "gen-dag-isel",
"Generate a DAG instruction selector"),
+ clEnumValN(GenFastISel, "gen-fast-isel",
+ "Generate a \"fast\" instruction selector"),
clEnumValN(GenSubtarget, "gen-subtarget",
"Generate subtarget enumerations"),
clEnumValN(GenIntrinsic, "gen-intrinsic",
@@ -177,6 +181,9 @@ int main(int argc, char **argv) {
case GenDAGISel:
DAGISelEmitter(Records).run(*Out);
break;
+ case GenFastISel:
+ FastISelEmitter(Records).run(*Out);
+ break;
case GenSubtarget:
SubtargetEmitter(Records).run(*Out);
break;