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[X86] Don't emit COPY_TO_REG to ABCD registers before EXTRACT_SUBREG of sub_8bit_hi 

I'm pretty sure that InstrEmitter::EmitSubregNode will take care of this itself by calling ConstrainForSubReg which in turn calls TRI->getSubClassWithSubReg.

I think Jakob Stoklund Olesen alluded to this in his commit message for r141207 which added the code to EmitSubregNode.

Differential Revision: https://reviews.llvm.org/D37843

llvm-svn: 313557
This commit is contained in:
Craig Topper 2017-09-18 19:21:19 +00:00
parent 27a357c9d9
commit b2155159a8
2 changed files with 19 additions and 56 deletions
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12
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
View File

@ -2966,18 +2966,6 @@ void X86DAGToDAGISel::Select(SDNode *Node) {
SDValue ShiftedImm = CurDAG->getTargetConstant(Mask >> 8, dl, MVT::i8); SDValue ShiftedImm = CurDAG->getTargetConstant(Mask >> 8, dl, MVT::i8);
SDValue Reg = N0.getOperand(0); SDValue Reg = N0.getOperand(0);
// Put the value in an ABCD register.
const TargetRegisterClass *TRC;
switch (N0.getSimpleValueType().SimpleTy) {
case MVT::i64: TRC = &X86::GR64_ABCDRegClass; break;
case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break;
case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
default: llvm_unreachable("Unsupported TEST operand type!");
}
SDValue RC = CurDAG->getTargetConstant(TRC->getID(), dl, MVT::i32);
Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl,
Reg.getValueType(), Reg, RC), 0);
// Extract the h-register. // Extract the h-register.
SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_8bit_hi, dl, SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_8bit_hi, dl,
MVT::i8, Reg); MVT::i8, Reg);

63
llvm/lib/Target/X86/X86InstrCompiler.td
View File

@ -1502,43 +1502,30 @@ def : Pat<(i8 (trunc GR16:$src)),
// h-register tricks // h-register tricks
def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))), def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
(EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)>,
sub_8bit_hi)>,
Requires<[Not64BitMode]>; Requires<[Not64BitMode]>;
def : Pat<(i8 (trunc (srl_su (i32 (anyext GR16:$src)), (i8 8)))), def : Pat<(i8 (trunc (srl_su (i32 (anyext GR16:$src)), (i8 8)))),
(EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)>,
sub_8bit_hi)>,
Requires<[Not64BitMode]>; Requires<[Not64BitMode]>;
def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))), def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
(EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)), (EXTRACT_SUBREG GR32:$src, sub_8bit_hi)>,
sub_8bit_hi)>,
Requires<[Not64BitMode]>; Requires<[Not64BitMode]>;
def : Pat<(srl GR16:$src, (i8 8)), def : Pat<(srl GR16:$src, (i8 8)),
(EXTRACT_SUBREG (EXTRACT_SUBREG
(MOVZX32rr8 (MOVZX32rr8 (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)),
(EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
sub_8bit_hi)),
sub_16bit)>, sub_16bit)>,
Requires<[Not64BitMode]>; Requires<[Not64BitMode]>;
def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))), def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
(MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, (MOVZX32rr8 (EXTRACT_SUBREG GR16:$src, sub_8bit_hi))>,
GR16_ABCD)),
sub_8bit_hi))>,
Requires<[Not64BitMode]>; Requires<[Not64BitMode]>;
def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))), def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
(MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, (MOVZX32rr8 (EXTRACT_SUBREG GR16:$src, sub_8bit_hi))>,
GR16_ABCD)),
sub_8bit_hi))>,
Requires<[Not64BitMode]>; Requires<[Not64BitMode]>;
def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)), def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
(MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src, sub_8bit_hi))>,
GR32_ABCD)),
sub_8bit_hi))>,
Requires<[Not64BitMode]>; Requires<[Not64BitMode]>;
def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)), def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
(MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src, sub_8bit_hi))>,
GR32_ABCD)),
sub_8bit_hi))>,
Requires<[Not64BitMode]>; Requires<[Not64BitMode]>;
// h-register tricks. // h-register tricks.
@ -1553,68 +1540,56 @@ def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)),
(SUBREG_TO_REG (SUBREG_TO_REG
(i64 0), (i64 0),
(MOVZX32_NOREXrr8 (MOVZX32_NOREXrr8
(EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)), (EXTRACT_SUBREG GR64:$src, sub_8bit_hi)),
sub_8bit_hi)),
sub_32bit)>; sub_32bit)>;
def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)), def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
(MOVZX32_NOREXrr8 (MOVZX32_NOREXrr8
(EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)), (EXTRACT_SUBREG GR32:$src, sub_8bit_hi))>,
sub_8bit_hi))>,
Requires<[In64BitMode]>; Requires<[In64BitMode]>;
def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)), def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
(MOVZX32_NOREXrr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, (MOVZX32_NOREXrr8 (EXTRACT_SUBREG GR32:$src, sub_8bit_hi))>,
GR32_ABCD)),
sub_8bit_hi))>,
Requires<[In64BitMode]>; Requires<[In64BitMode]>;
def : Pat<(srl GR16:$src, (i8 8)), def : Pat<(srl GR16:$src, (i8 8)),
(EXTRACT_SUBREG (EXTRACT_SUBREG
(MOVZX32_NOREXrr8 (MOVZX32_NOREXrr8
(EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)),
sub_8bit_hi)),
sub_16bit)>, sub_16bit)>,
Requires<[In64BitMode]>; Requires<[In64BitMode]>;
def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))), def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
(MOVZX32_NOREXrr8 (MOVZX32_NOREXrr8
(EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), (EXTRACT_SUBREG GR16:$src, sub_8bit_hi))>,
sub_8bit_hi))>,
Requires<[In64BitMode]>; Requires<[In64BitMode]>;
def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))), def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
(MOVZX32_NOREXrr8 (MOVZX32_NOREXrr8
(EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), (EXTRACT_SUBREG GR16:$src, sub_8bit_hi))>,
sub_8bit_hi))>,
Requires<[In64BitMode]>; Requires<[In64BitMode]>;
def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))), def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))),
(SUBREG_TO_REG (SUBREG_TO_REG
(i64 0), (i64 0),
(MOVZX32_NOREXrr8 (MOVZX32_NOREXrr8
(EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)),
sub_8bit_hi)),
sub_32bit)>; sub_32bit)>;
def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))), def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))),
(SUBREG_TO_REG (SUBREG_TO_REG
(i64 0), (i64 0),
(MOVZX32_NOREXrr8 (MOVZX32_NOREXrr8
(EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)),
sub_8bit_hi)),
sub_32bit)>; sub_32bit)>;
// h-register extract and store. // h-register extract and store.
def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst), def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst),
(MOV8mr_NOREX (MOV8mr_NOREX
addr:$dst, addr:$dst,
(EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)), (EXTRACT_SUBREG GR64:$src, sub_8bit_hi))>;
sub_8bit_hi))>;
def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst), def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst),
(MOV8mr_NOREX (MOV8mr_NOREX
addr:$dst, addr:$dst,
(EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)), (EXTRACT_SUBREG GR32:$src, sub_8bit_hi))>,
sub_8bit_hi))>,
Requires<[In64BitMode]>; Requires<[In64BitMode]>;
def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst), def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst),
(MOV8mr_NOREX (MOV8mr_NOREX
addr:$dst, addr:$dst,
(EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), (EXTRACT_SUBREG GR16:$src, sub_8bit_hi))>,
sub_8bit_hi))>,
Requires<[In64BitMode]>; Requires<[In64BitMode]>;