forked from OSchip/llvm-project
[SelectionDAG] Replace the Chain in LOAD->VP_LOAD widening
The introduction of this legalization, D111248, forgot to replace the old chain with the new. This could manifest itself in the old (illegally-typed) value remaining in the DAG, though the simple test cases didn't catch this. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D113561
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@ -4214,9 +4214,16 @@ SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) {
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SDValue EVL =
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DAG.getVScale(DL, EVLVT, APInt(EVLVT.getScalarSizeInBits(), NumVTElts));
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const auto *MMO = LD->getMemOperand();
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return DAG.getLoadVP(WideVT, DL, LD->getChain(), LD->getBasePtr(), Mask,
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EVL, MMO->getPointerInfo(), MMO->getAlign(),
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MMO->getFlags(), MMO->getAAInfo());
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SDValue NewLoad =
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DAG.getLoadVP(WideVT, DL, LD->getChain(), LD->getBasePtr(), Mask, EVL,
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MMO->getPointerInfo(), MMO->getAlign(), MMO->getFlags(),
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MMO->getAAInfo());
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// Modified the chain - switch anything that used the old chain to use
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// the new one.
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ReplaceValueWith(SDValue(N, 1), NewLoad.getValue(1));
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return NewLoad;
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}
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report_fatal_error("Unable to widen vector load");
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@ -31,3 +31,19 @@ define <vscale x 5 x half> @load_nxv5f16(<vscale x 5 x half>* %ptr) {
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%v = load <vscale x 5 x half>, <vscale x 5 x half>* %ptr
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ret <vscale x 5 x half> %v
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}
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define <vscale x 7 x half> @load_nxv7f16(<vscale x 7 x half>* %ptr, <vscale x 7 x half>* %out) {
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; CHECK-LABEL: load_nxv7f16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: csrr a2, vlenb
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; CHECK-NEXT: srli a2, a2, 3
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; CHECK-NEXT: slli a3, a2, 3
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; CHECK-NEXT: sub a2, a3, a2
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; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu
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; CHECK-NEXT: vle16.v v8, (a0)
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; CHECK-NEXT: vse16.v v8, (a1)
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; CHECK-NEXT: ret
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%v = load <vscale x 7 x half>, <vscale x 7 x half>* %ptr
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store <vscale x 7 x half> %v, <vscale x 7 x half>* %out
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ret <vscale x 7 x half> %v
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}
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