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[Hexagon] Add support for getRegisterByName. 

Support required to build the Hexagon Linux kernel.

Differential Revision: https://reviews.llvm.org/D51363

llvm-svn: 341238
This commit is contained in:
Sid Manning 2018-08-31 19:08:23 +00:00
parent 7975e274da
commit b1c9813042
3 changed files with 72 additions and 0 deletions
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46
llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
View File

@ -22,6 +22,7 @@
#include "llvm/ADT/APInt.h" #include "llvm/ADT/APInt.h"
#include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/SmallVector.h" #include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringSwitch.h"
#include "llvm/CodeGen/CallingConvLower.h" #include "llvm/CodeGen/CallingConvLower.h"
#include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFunction.h"
@ -240,6 +241,51 @@ bool HexagonTargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
return true; return true;
} }
unsigned HexagonTargetLowering::getRegisterByName(const char* RegName, EVT VT,
SelectionDAG &DAG) const {
unsigned Reg = StringSwitch<unsigned>(RegName)
.Case("r0", Hexagon::R0)
.Case("r1", Hexagon::R1)
.Case("r2", Hexagon::R2)
.Case("r3", Hexagon::R3)
.Case("r4", Hexagon::R4)
.Case("r5", Hexagon::R5)
.Case("r6", Hexagon::R6)
.Case("r7", Hexagon::R7)
.Case("r8", Hexagon::R8)
.Case("r9", Hexagon::R9)
.Case("r10", Hexagon::R10)
.Case("r11", Hexagon::R11)
.Case("r12", Hexagon::R12)
.Case("r13", Hexagon::R13)
.Case("r14", Hexagon::R14)
.Case("r15", Hexagon::R15)
.Case("r16", Hexagon::R16)
.Case("r17", Hexagon::R17)
.Case("r18", Hexagon::R18)
.Case("r19", Hexagon::R19)
.Case("r20", Hexagon::R20)
.Case("r21", Hexagon::R21)
.Case("r22", Hexagon::R22)
.Case("r23", Hexagon::R23)
.Case("r24", Hexagon::R24)
.Case("r25", Hexagon::R25)
.Case("r26", Hexagon::R26)
.Case("r27", Hexagon::R27)
.Case("r28", Hexagon::R28)
.Case("r29", Hexagon::R29)
.Case("sp", Hexagon::R29)
.Case("r30", Hexagon::R30)
.Case("fp", Hexagon::R30)
.Case("r31", Hexagon::R31)
.Case("sp", Hexagon::R31)
.Default(0);
if (Reg)
return Reg;
report_fatal_error("Invalid register name global variable");
}
/// LowerCallResult - Lower the result values of an ISD::CALL into the /// LowerCallResult - Lower the result values of an ISD::CALL into the
/// appropriate copies out of appropriate physical registers. This assumes that /// appropriate copies out of appropriate physical registers. This assumes that
/// Chain/Glue are the input chain/glue to use, and that TheCall is the call /// Chain/Glue are the input chain/glue to use, and that TheCall is the call

3
llvm/lib/Target/Hexagon/HexagonISelLowering.h
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@ -223,6 +223,9 @@ namespace HexagonISD {
bool mayBeEmittedAsTailCall(const CallInst *CI) const override; bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
unsigned getRegisterByName(const char* RegName, EVT VT,
SelectionDAG &DAG) const override;
/// If a physical register, this returns the register that receives the /// If a physical register, this returns the register that receives the
/// exception address on entry to an EH pad. /// exception address on entry to an EH pad.
unsigned unsigned

23
llvm/test/CodeGen/Hexagon/namedreg.ll Normal file
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@ -0,0 +1,23 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
define dso_local i32 @r19f() #0 {
entry:
%0 = call i32 @llvm.read_register.i32(metadata !0)
ret i32 %0
}
; Function Attrs: noinline nounwind optnone
define dso_local i32 @spf() #0 {
entry:
%0 = call i32 @llvm.read_register.i32(metadata !1)
ret i32 %0
}
declare i32 @llvm.read_register.i32(metadata) #1
!llvm.named.register.r19 = !{!0}
!llvm.named.register.sp = !{!1}
!0 = !{!"r19"}
!1 = !{!"sp"}
; CHECK: r0 = r19
; CHECK: r0 = r29