forked from OSchip/llvm-project
enhance llvm-mc -show-inst to print the enum of an instruction, like so:
testb %al, %al ## <MCInst #2412 TEST8rr ## <MCOperand Reg:2> ## <MCOperand Reg:2>> jne LBB1_7 ## <MCInst #938 JNE_1 ## <MCOperand Expr:(LBB1_7)>> llvm-svn: 95935
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@ -25,10 +25,15 @@ using namespace llvm;
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// Include the auto-generated portion of the assembly writer.
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#define MachineInstr MCInst
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#define GET_INSTRUCTION_NAME
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#include "X86GenAsmWriter.inc"
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#undef MachineInstr
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void X86ATTInstPrinter::printInst(const MCInst *MI) { printInstruction(MI); }
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StringRef X86ATTInstPrinter::getOpcodeName(unsigned Opcode) const {
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return getInstructionName(Opcode);
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}
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void X86ATTInstPrinter::printSSECC(const MCInst *MI, unsigned Op) {
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switch (MI->getOperand(Op).getImm()) {
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@ -26,11 +26,12 @@ public:
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virtual void printInst(const MCInst *MI);
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virtual StringRef getOpcodeName(unsigned Opcode) const;
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// Autogenerated by tblgen.
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void printInstruction(const MCInst *MI);
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static const char *getRegisterName(unsigned RegNo);
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static const char *getInstructionName(unsigned Opcode);
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void printOperand(const MCInst *MI, unsigned OpNo);
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void printMemReference(const MCInst *MI, unsigned Op);
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@ -24,10 +24,14 @@ using namespace llvm;
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// Include the auto-generated portion of the assembly writer.
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#define MachineInstr MCInst
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#define GET_INSTRUCTION_NAME
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#include "X86GenAsmWriter1.inc"
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#undef MachineInstr
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void X86IntelInstPrinter::printInst(const MCInst *MI) { printInstruction(MI); }
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StringRef X86IntelInstPrinter::getOpcodeName(unsigned Opcode) const {
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return getInstructionName(Opcode);
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}
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void X86IntelInstPrinter::printSSECC(const MCInst *MI, unsigned Op) {
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switch (MI->getOperand(Op).getImm()) {
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@ -26,10 +26,12 @@ public:
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: MCInstPrinter(O, MAI) {}
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virtual void printInst(const MCInst *MI);
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virtual StringRef getOpcodeName(unsigned Opcode) const;
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// Autogenerated by tblgen.
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void printInstruction(const MCInst *MI);
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static const char *getRegisterName(unsigned RegNo);
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static const char *getInstructionName(unsigned Opcode);
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void printOperand(const MCInst *MI, unsigned OpNo,
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@ -494,11 +494,55 @@ void AsmWriterEmitter::EmitGetRegisterName(raw_ostream &O) {
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<< "}\n";
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}
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void AsmWriterEmitter::EmitGetInstructionName(raw_ostream &O) {
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CodeGenTarget Target;
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Record *AsmWriter = Target.getAsmWriter();
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std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
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std::vector<const CodeGenInstruction*> NumberedInstructions;
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Target.getInstructionsByEnumValue(NumberedInstructions);
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StringToOffsetTable StringTable;
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O <<
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"\n\n#ifdef GET_INSTRUCTION_NAME\n"
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"#undef GET_INSTRUCTION_NAME\n\n"
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"/// getInstructionName: This method is automatically generated by tblgen\n"
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"/// from the instruction set description. This returns the enum name of the\n"
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"/// specified instruction.\n"
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"const char *" << Target.getName() << ClassName
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<< "::getInstructionName(unsigned Opcode) {\n"
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<< " assert(Opcode < " << NumberedInstructions.size()
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<< " && \"Invalid instruction number!\");\n"
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<< "\n"
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<< " static const unsigned InstAsmOffset[] = {";
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for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
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const CodeGenInstruction &Inst = *NumberedInstructions[i];
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std::string AsmName = Inst.TheDef->getName();
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if ((i % 14) == 0)
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O << "\n ";
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O << StringTable.GetOrAddStringOffset(AsmName) << ", ";
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}
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O << "0\n"
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<< " };\n"
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<< "\n";
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O << " const char *Strs =\n";
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StringTable.EmitString(O);
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O << ";\n";
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O << " return Strs+InstAsmOffset[Opcode];\n"
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<< "}\n\n#endif\n";
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}
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void AsmWriterEmitter::run(raw_ostream &O) {
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EmitSourceFileHeader("Assembly Writer Source Fragment", O);
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EmitPrintInstruction(O);
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EmitGetRegisterName(O);
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EmitGetInstructionName(O);
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}
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@ -37,6 +37,7 @@ namespace llvm {
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private:
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void EmitPrintInstruction(raw_ostream &o);
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void EmitGetRegisterName(raw_ostream &o);
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void EmitGetInstructionName(raw_ostream &o);
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AsmWriterInst *getAsmWriterInstByID(unsigned ID) const {
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assert(ID < NumberedInstructions.size());
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