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Add variants of VST2, VST3 and VST4 with address register writeback, and 

rewrite the existing VST3 and VST4 instructions to use the same classes as
the others.

llvm-svn: 99093
This commit is contained in:
Bob Wilson 2010-03-20 21:45:18 +00:00
parent 89ba42c4ce
commit b18adef4ad
1 changed files with 80 additions and 30 deletions
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110
llvm/lib/Target/ARM/ARMInstrNEON.td
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@ -616,21 +616,45 @@ def VST2q8 : VST2Q<0b0000, "8">;
def VST2q16 : VST2Q<0b0100, "16">;
def VST2q32 : VST2Q<0b1000, "32">;
// ...with address register writeback:
class VST2DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
: NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
(ins addrmode6:$addr, DPR:$src1, DPR:$src2),
IIC_VST, "vst2", Dt, "\\{$src1, $src2\\}, $addr",
"$addr.addr = $wb", []>;
class VST2QWB<bits<4> op7_4, string Dt>
: NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
(ins addrmode6:$addr,
DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
IIC_VST, "vst2", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr",
"$addr.addr = $wb", []>;
def VST2d8_UPD : VST2DWB<0b1000, 0b0000, "8">;
def VST2d16_UPD : VST2DWB<0b1000, 0b0100, "16">;
def VST2d32_UPD : VST2DWB<0b1000, 0b1000, "32">;
def VST2d64_UPD : NLdSt<0,0b00,0b1010,0b1100, (outs GPR:$wb),
(ins addrmode6:$addr,
DPR:$src1, DPR:$src2), IIC_VST,
"vst1", "64", "\\{$src1, $src2\\}, $addr",
"$addr.addr = $wb", []>;
def VST2q8_UPD : VST2QWB<0b0000, "8">;
def VST2q16_UPD : VST2QWB<0b0100, "16">;
def VST2q32_UPD : VST2QWB<0b1000, "32">;
// ...with double-spaced registers (for disassembly only):
def VST2b8 : VST2D<0b1001, 0b0000, "8">;
def VST2b16 : VST2D<0b1001, 0b0100, "16">;
def VST2b32 : VST2D<0b1001, 0b1000, "32">;
def VST2b8_UPD : VST2DWB<0b1001, 0b0000, "8">;
def VST2b16_UPD : VST2DWB<0b1001, 0b0100, "16">;
def VST2b32_UPD : VST2DWB<0b1001, 0b1000, "32">;
// VST3 : Vector Store (multiple 3-element structures)
class VST3D<bits<4> op11_8, bits<4> op7_4, string Dt>
: NLdSt<0, 0b00, op11_8, op7_4, (outs),
(ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3), IIC_VST,
"vst3", Dt, "\\{$src1, $src2, $src3\\}, $addr", "", []>;
class VST3WB<bits<4> op7_4, string Dt>
: NLdSt<0,0b00,0b0101,op7_4, (outs GPR:$wb),
(ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3), IIC_VST,
"vst3", Dt, "\\{$src1, $src2, $src3\\}, $addr",
"$addr.addr = $wb", []>;
def VST3d8 : VST3D<0b0100, 0b0000, "8">;
def VST3d16 : VST3D<0b0100, 0b0100, "16">;
@ -640,20 +664,35 @@ def VST3d64 : NLdSt<0,0b00,0b0110,0b1100, (outs),
IIC_VST,
"vst1", "64", "\\{$src1, $src2, $src3\\}, $addr", "", []>;
// ...with double-spaced registers:
// ...with address register writeback:
class VST3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
: NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
(ins addrmode6:$addr,
DPR:$src1, DPR:$src2, DPR:$src3), IIC_VST,
"vst3", Dt, "\\{$src1, $src2, $src3\\}, $addr",
"$addr.addr = $wb", []>;
def VST3d8_UPD : VST3DWB<0b0100, 0b0000, "8">;
def VST3d16_UPD : VST3DWB<0b0100, 0b0100, "16">;
def VST3d32_UPD : VST3DWB<0b0100, 0b1000, "32">;
def VST3d64_UPD : NLdSt<0,0b00,0b0110,0b1100, (outs GPR:$wb),
(ins addrmode6:$addr,
DPR:$src1, DPR:$src2, DPR:$src3), IIC_VST,
"vst1", "64", "\\{$src1, $src2, $src3\\}, $addr",
"$addr.addr = $wb", []>;
// ...with double-spaced registers (non-updating versions for disassembly only):
def VST3q8 : VST3D<0b0101, 0b0000, "8">;
def VST3q16 : VST3D<0b0101, 0b0100, "16">;
def VST3q32 : VST3D<0b0101, 0b1000, "32">;
def VST3q8_UPD : VST3DWB<0b0101, 0b0000, "8">;
def VST3q16_UPD : VST3DWB<0b0101, 0b0100, "16">;
def VST3q32_UPD : VST3DWB<0b0101, 0b1000, "32">;
// vst3 to double-spaced even registers.
def VST3q8_UPD : VST3WB<0b0000, "8">;
def VST3q16_UPD : VST3WB<0b0100, "16">;
def VST3q32_UPD : VST3WB<0b1000, "32">;
// vst3 to double-spaced odd registers.
def VST3q8odd_UPD : VST3WB<0b0000, "8">;
def VST3q16odd_UPD : VST3WB<0b0100, "16">;
def VST3q32odd_UPD : VST3WB<0b1000, "32">;
// ...alternate versions to be allocated odd register numbers:
def VST3q8odd_UPD : VST3DWB<0b0101, 0b0000, "8">;
def VST3q16odd_UPD : VST3DWB<0b0101, 0b0100, "16">;
def VST3q32odd_UPD : VST3DWB<0b0101, 0b1000, "32">;
// VST4 : Vector Store (multiple 4-element structures)
class VST4D<bits<4> op11_8, bits<4> op7_4, string Dt>
@ -661,11 +700,6 @@ class VST4D<bits<4> op11_8, bits<4> op7_4, string Dt>
(ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
IIC_VST, "vst4", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr",
"", []>;
class VST4WB<bits<4> op7_4, string Dt>
: NLdSt<0,0b00,0b0001,op7_4, (outs GPR:$wb),
(ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
IIC_VST, "vst4", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr",
"$addr.addr = $wb", []>;
def VST4d8 : VST4D<0b0000, 0b0000, "8">;
def VST4d16 : VST4D<0b0000, 0b0100, "16">;
@ -676,20 +710,36 @@ def VST4d64 : NLdSt<0,0b00,0b0010,0b1100, (outs),
"vst1", "64", "\\{$src1, $src2, $src3, $src4\\}, $addr",
"", []>;
// ...with double-spaced registers:
// ...with address register writeback:
class VST4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
: NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
(ins addrmode6:$addr,
DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST,
"vst4", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr",
"$addr.addr = $wb", []>;
def VST4d8_UPD : VST4DWB<0b0000, 0b0000, "8">;
def VST4d16_UPD : VST4DWB<0b0000, 0b0100, "16">;
def VST4d32_UPD : VST4DWB<0b0000, 0b1000, "32">;
def VST4d64_UPD : NLdSt<0,0b00,0b0010,0b1100, (outs GPR:$wb),
(ins addrmode6:$addr,
DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST,
"vst1", "64",
"\\{$src1, $src2, $src3, $src4\\}, $addr",
"$addr.addr = $wb", []>;
// ...with double-spaced registers (non-updating versions for disassembly only):
def VST4q8 : VST4D<0b0001, 0b0000, "8">;
def VST4q16 : VST4D<0b0001, 0b0100, "16">;
def VST4q32 : VST4D<0b0001, 0b1000, "32">;
def VST4q8_UPD : VST4DWB<0b0001, 0b0000, "8">;
def VST4q16_UPD : VST4DWB<0b0001, 0b0100, "16">;
def VST4q32_UPD : VST4DWB<0b0001, 0b1000, "32">;
// vst4 to double-spaced even registers.
def VST4q8_UPD : VST4WB<0b0000, "8">;
def VST4q16_UPD : VST4WB<0b0100, "16">;
def VST4q32_UPD : VST4WB<0b1000, "32">;
// vst4 to double-spaced odd registers.
def VST4q8odd_UPD : VST4WB<0b0000, "8">;
def VST4q16odd_UPD : VST4WB<0b0100, "16">;
def VST4q32odd_UPD : VST4WB<0b1000, "32">;
// ...alternate versions to be allocated odd register numbers:
def VST4q8odd_UPD : VST4DWB<0b0001, 0b0000, "8">;
def VST4q16odd_UPD : VST4DWB<0b0001, 0b0100, "16">;
def VST4q32odd_UPD : VST4DWB<0b0001, 0b1000, "32">;
// VST1LN : Vector Store (single element from one lane)
// FIXME: Not yet implemented.