forked from OSchip/llvm-project
[LegalizeVectorTypes] Allow single loads and stores for more short vectors
When lowering a load or store for TypeWidenVector, the type legalizer would use a single load or store if the associated integer type was legal or promoted. E.g. it loads a v4i8 as an i32 if i32 is legal/promotable. (See https://reviews.llvm.org/rL236528 for reference.) This applies that behaviour to vector types. If the vector type is TypePromoteInteger, the element type is going to be TypePromoteInteger as well, which will lead to have a single promoting load rather than N individual promoting loads. For instance, if we have a v3i1, we would now have a load of v4i1 instead of 3 loads of i1. Patch by Guillaume Marques. Thanks! Differential Revision: https://reviews.llvm.org/D56201 llvm-svn: 357120
This commit is contained in:
Justin Bogner
parent
ee9f2ae5b9
commit
b1650f0da9
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@ -4380,6 +4380,8 @@ static EVT FindMemType(SelectionDAG& DAG, const TargetLowering &TLI,
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isPowerOf2_32(WidenWidth / MemVTWidth) &&
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(MemVTWidth <= Width ||
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(Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
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if (MemVTWidth == WidenWidth)
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return MemVT;
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RetVT = MemVT;
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break;
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}
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@ -4391,7 +4393,10 @@ static EVT FindMemType(SelectionDAG& DAG, const TargetLowering &TLI,
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VT >= (unsigned)MVT::FIRST_VECTOR_VALUETYPE; --VT) {
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EVT MemVT = (MVT::SimpleValueType) VT;
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unsigned MemVTWidth = MemVT.getSizeInBits();
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if (TLI.isTypeLegal(MemVT) && WidenEltVT == MemVT.getVectorElementType() &&
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auto Action = TLI.getTypeAction(*DAG.getContext(), MemVT);
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if ((Action == TargetLowering::TypeLegal ||
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Action == TargetLowering::TypePromoteInteger) &&
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WidenEltVT == MemVT.getVectorElementType() &&
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(WidenWidth % MemVTWidth) == 0 &&
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isPowerOf2_32(WidenWidth / MemVTWidth) &&
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(MemVTWidth <= Width ||
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@ -1239,11 +1239,13 @@ SDValue R600TargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
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SDLoc DL(Op);
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const bool TruncatingStore = StoreNode->isTruncatingStore();
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// Neither LOCAL nor PRIVATE can do vectors at the moment
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if ((AS == AMDGPUAS::LOCAL_ADDRESS || AS == AMDGPUAS::PRIVATE_ADDRESS) &&
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if ((AS == AMDGPUAS::LOCAL_ADDRESS || AS == AMDGPUAS::PRIVATE_ADDRESS ||
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TruncatingStore) &&
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VT.isVector()) {
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if ((AS == AMDGPUAS::PRIVATE_ADDRESS) &&
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StoreNode->isTruncatingStore()) {
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if ((AS == AMDGPUAS::PRIVATE_ADDRESS) && TruncatingStore) {
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// Add an extra level of chain to isolate this vector
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SDValue NewChain = DAG.getNode(AMDGPUISD::DUMMY_CHAIN, DL, MVT::Other, Chain);
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// TODO: can the chain be replaced without creating a new store?
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@ -1269,7 +1271,7 @@ SDValue R600TargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
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if (AS == AMDGPUAS::GLOBAL_ADDRESS) {
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// It is beneficial to create MSKOR here instead of combiner to avoid
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// artificial dependencies introduced by RMW
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if (StoreNode->isTruncatingStore()) {
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if (TruncatingStore) {
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assert(VT.bitsLE(MVT::i32));
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SDValue MaskConstant;
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if (MemVT == MVT::i8) {
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@ -1309,8 +1311,8 @@ SDValue R600TargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
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// Convert pointer from byte address to dword address.
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Ptr = DAG.getNode(AMDGPUISD::DWORDADDR, DL, PtrVT, DWordAddr);
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if (StoreNode->isTruncatingStore() || StoreNode->isIndexed()) {
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llvm_unreachable("Truncated and indexed stores not supported yet");
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if (StoreNode->isIndexed()) {
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llvm_unreachable("Indexed stores not supported yet");
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} else {
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Chain = DAG.getStore(Chain, DL, Value, Ptr, StoreNode->getMemOperand());
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}
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@ -29,7 +29,8 @@ entry:
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; FUNC-LABEL: {{^}}constant_load_v3i16:
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; GCN: s_load_dwordx2 s
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; EG-DAG: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1
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; EG-DAG: VTX_READ_16 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1
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; EG-DAG: VTX_READ_16 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 2, #1
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; EG-DAG: VTX_READ_16 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 4, #1
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define amdgpu_kernel void @constant_load_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> addrspace(4)* %in) {
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entry:
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@ -186,15 +187,11 @@ define amdgpu_kernel void @constant_sextload_v2i16_to_v2i32(<2 x i32> addrspace(
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; EG-DAG: MEM_RAT_CACHELESS STORE_RAW [[ST_LO:T[0-9]]].XY, {{T[0-9].[XYZW]}},
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; EG-DAG: MEM_RAT_CACHELESS STORE_RAW [[ST_HI:T[0-9]]].X, {{T[0-9].[XYZW]}},
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; EG: CF_END
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; EG-DAG: VTX_READ_32 [[DST_LO:T[0-9]\.[XYZW]]], {{T[0-9]\.[XYZW]}}, 0, #1
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; EG-DAG: VTX_READ_16 [[DST_HI:T[0-9]\.[XYZW]]], {{T[0-9]\.[XYZW]}}, 4, #1
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; TODO: This should use DST, but for some there are redundant MOVs
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; EG-DAG: LSHR {{[* ]*}}[[ST_LO]].Y, {{T[0-9]\.[XYZW]}}, literal
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; EG-DAG: VTX_READ_16 [[ST_LO]].X, [[SRC:T[0-9]\.[XYZW]]], 0, #1
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; EG-DAG: VTX_READ_16 {{T[0-9]\.[XYZW]}}, [[SRC]], 2, #1
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; EG-DAG: VTX_READ_16 [[ST_HI]].X, [[SRC]], 4, #1
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; EG-DAG: LSHR {{[* ]*}}{{T[0-9]\.[XYZW]}}, {{T[0-9]\.[XYZW]}}, literal
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; EG-DAG: 16
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; EG-DAG: AND_INT {{[* ]*}}[[ST_LO]].X, {{T[0-9]\.[XYZW]}}, literal
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; EG-DAG: AND_INT {{[* ]*}}[[ST_HI]].X, {{T[0-9]\.[XYZW]}}, literal
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; EG-DAG: 65535
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; EG-DAG: 65535
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define amdgpu_kernel void @constant_zextload_v3i16_to_v3i32(<3 x i32> addrspace(1)* %out, <3 x i16> addrspace(4)* %in) {
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entry:
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%ld = load <3 x i16>, <3 x i16> addrspace(4)* %in
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@ -209,11 +206,12 @@ entry:
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; EG-DAG: MEM_RAT_CACHELESS STORE_RAW [[ST_LO:T[0-9]]].XY, {{T[0-9].[XYZW]}},
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; EG-DAG: MEM_RAT_CACHELESS STORE_RAW [[ST_HI:T[0-9]]].X, {{T[0-9].[XYZW]}},
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; v3i16 is naturally 8 byte aligned
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; EG-DAG: VTX_READ_32 [[DST_HI:T[0-9]\.[XYZW]]], [[PTR:T[0-9]\.[XYZW]]], 0, #1
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; EG-DAG: VTX_READ_16 [[DST_LO:T[0-9]\.[XYZW]]], {{T[0-9]\.[XYZW]}}, 4, #1
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; EG-DAG: ASHR {{[* ]*}}[[ST_LO]].Y, {{T[0-9]\.[XYZW]}}, literal
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; EG-DAG: BFE_INT {{[* ]*}}[[ST_LO]].X, {{T[0-9]\.[XYZW]}}, 0.0, literal
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; EG-DAG: BFE_INT {{[* ]*}}[[ST_HI]].X, {{T[0-9]\.[XYZW]}}, 0.0, literal
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; EG-DAG: VTX_READ_16 [[ST_LO]].X, [[SRC:T[0-9]\.[XYZW]]], 0, #1
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; EG-DAG: VTX_READ_16 [[DST_MID:T[0-9]\.[XYZW]]], [[SRC]], 2, #1
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; EG-DAG: VTX_READ_16 [[ST_HI]].X, [[SRC]], 4, #1
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; EG-DAG: BFE_INT {{[* ]*}}[[ST_LO]].X, [[ST_LO]].X, 0.0, literal
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; EG-DAG: BFE_INT {{[* ]*}}[[ST_LO]].Y, [[DST_MID]], 0.0, literal
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; EG-DAG: BFE_INT {{[* ]*}}[[ST_HI]].X, [[ST_HI]].X, 0.0, literal
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; EG-DAG: 16
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; EG-DAG: 16
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define amdgpu_kernel void @constant_sextload_v3i16_to_v3i32(<3 x i32> addrspace(1)* %out, <3 x i16> addrspace(4)* %in) {
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@ -34,7 +34,8 @@ entry:
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; GCN-NOHSA: buffer_load_dwordx2 v
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; GCN-HSA: flat_load_dwordx2 v
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; EGCM-DAG: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1
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; EGCM-DAG: VTX_READ_16 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1
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; EGCM-DAG: VTX_READ_16 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 2, #1
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; EGCM-DAG: VTX_READ_16 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 4, #1
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define amdgpu_kernel void @global_load_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> addrspace(1)* %in) {
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entry:
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@ -195,10 +196,9 @@ define amdgpu_kernel void @global_sextload_v2i16_to_v2i32(<2 x i32> addrspace(1)
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; CM: MEM_RAT_CACHELESS STORE_DWORD [[ST_HI:T[0-9]]].X, {{T[0-9]\.[XYZW]}}
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; EG: MEM_RAT_CACHELESS STORE_RAW [[ST_HI:T[0-9]]].X, {{T[0-9]\.[XYZW]}},
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; EG: MEM_RAT_CACHELESS STORE_RAW [[ST_LO:T[0-9]]].XY, {{T[0-9]\.[XYZW]}},
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; EGCM-DAG: VTX_READ_32 [[DST_LO:T[0-9]\.[XYZW]]], {{T[0-9]\.[XYZW]}}, 0, #1
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; EGCM-DAG: VTX_READ_16 [[DST_HI:T[0-9]\.[XYZW]]], {{T[0-9]\.[XYZW]}}, 4, #1
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; TODO: This should use DST, but for some there are redundant MOVs
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; EGCM: LSHR {{[* ]*}}[[ST_LO]].Y, {{T[0-9]\.[XYZW]}}, literal
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; EGCM-DAG: VTX_READ_16 [[ST_LO]].X, [[SRC:T[0-9]\.[XYZW]]], 0, #1
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; EGCM-DAG: VTX_READ_16 {{T[0-9]\.[XYZW]}}, [[SRC]], 2, #1
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; EGCM-DAG: VTX_READ_16 [[ST_HI]].X, [[SRC]], 4, #1
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; EGCM: 16
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define amdgpu_kernel void @global_zextload_v3i16_to_v3i32(<3 x i32> addrspace(1)* %out, <3 x i16> addrspace(1)* %in) {
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entry:
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@ -216,11 +216,11 @@ entry:
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; CM: MEM_RAT_CACHELESS STORE_DWORD [[ST_HI:T[0-9]]].X, {{T[0-9]\.[XYZW]}}
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; EG: MEM_RAT_CACHELESS STORE_RAW [[ST_HI:T[0-9]]].X, {{T[0-9]\.[XYZW]}},
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; EG: MEM_RAT_CACHELESS STORE_RAW [[ST_LO:T[0-9]]].XY, {{T[0-9]\.[XYZW]}},
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; EGCM-DAG: VTX_READ_32 [[DST_LO:T[0-9]\.[XYZW]]], {{T[0-9].[XYZW]}}, 0, #1
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; EGCM-DAG: VTX_READ_16 [[DST_HI:T[0-9]\.[XYZW]]], {{T[0-9].[XYZW]}}, 4, #1
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; TODO: This should use DST, but for some there are redundant MOVs
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; EGCM-DAG: ASHR {{[* ]*}}[[ST_LO]].Y, {{T[0-9]\.[XYZW]}}, literal
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; EGCM-DAG: BFE_INT {{[* ]*}}[[ST_LO]].X, {{T[0-9]\.[XYZW]}}, 0.0, literal
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; EGCM-DAG: VTX_READ_16 [[DST_LO:T[0-9]\.[XYZW]]], [[SRC:T[0-9].[XYZW]]], 0, #1
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; EGCM-DAG: VTX_READ_16 [[DST_MID:T[0-9]\.[XYZW]]], [[SRC]], 2, #1
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; EGCM-DAG: VTX_READ_16 [[DST_HI:T[0-9]\.[XYZW]]], [[SRC]], 4, #1
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; EGCM-DAG: BFE_INT {{[* ]*}}[[ST_LO]].X, [[DST_LO]], 0.0, literal
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; EGCM-DAG: BFE_INT {{[* ]*}}[[ST_LO]].Y, [[DST_MID]], 0.0, literal
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; EGCM-DAG: BFE_INT {{[* ]*}}[[ST_HI]].X, [[DST_HI]], 0.0, literal
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; EGCM-DAG: 16
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; EGCM-DAG: 16
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@ -52,7 +52,7 @@ entry:
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; GCN-DAG: ds_write_b16
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; EG-DAG: LDS_USHORT_READ_RET
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; EG-DAG: LDS_READ_RET
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; EG-DAG: LDS_USHORT_READ_RET
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define amdgpu_kernel void @local_load_v3i16(<3 x i16> addrspace(3)* %out, <3 x i16> addrspace(3)* %in) {
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entry:
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%ld = load <3 x i16>, <3 x i16> addrspace(3)* %in
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@ -235,7 +235,9 @@ define amdgpu_kernel void @local_sextload_v2i16_to_v2i32(<2 x i32> addrspace(3)*
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; GCN-DAG: ds_write_b32
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; GCN-DAG: ds_write_b64
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; EG: LDS_READ_RET
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; EG: LDS_USHORT_READ_RET
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; EG: LDS_USHORT_READ_RET
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; EG: LDS_USHORT_READ_RET
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define amdgpu_kernel void @local_local_zextload_v3i16_to_v3i32(<3 x i32> addrspace(3)* %out, <3 x i16> addrspace(3)* %in) {
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entry:
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%ld = load <3 x i16>, <3 x i16> addrspace(3)* %in
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@ -252,7 +254,9 @@ entry:
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; GCN-DAG: ds_write_b32
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; GCN-DAG: ds_write_b64
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; EG: LDS_READ_RET
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; EG: LDS_USHORT_READ_RET
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; EG: LDS_USHORT_READ_RET
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; EG: LDS_USHORT_READ_RET
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; EG-DAG: BFE_INT
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; EG-DAG: BFE_INT
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; EG-DAG: BFE_INT
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@ -0,0 +1,70 @@
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.2 | FileCheck %s
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; widen a v3i1 to v4i1 to do a vector load/store. We would previously
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; reconstruct the said v3i1 from the first element of the vector by filling all
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; the lanes of the vector with that first element, which was obviously wrong.
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; This was done in the type-legalizing of the DAG, when legalizing the load.
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; Function Attrs: argmemonly nounwind readonly
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declare <3 x i32> @llvm.masked.load.v3i32.p1v3i32(<3 x i32> addrspace(1)*, i32, <3 x i1>, <3 x i32>)
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; Function Attrs: argmemonly nounwind
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declare void @llvm.masked.store.v3i32.p1v3i32(<3 x i32>, <3 x i32> addrspace(1)*, i32, <3 x i1>)
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define <3 x i32> @masked_load_v3(i32 addrspace(1)*, <3 x i1>) {
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entry:
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%2 = bitcast i32 addrspace(1)* %0 to <3 x i32> addrspace(1)*
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%3 = call <3 x i32> @llvm.masked.load.v3i32.p1v3i32(<3 x i32> addrspace(1)* %2, i32 4, <3 x i1> %1, <3 x i32> undef)
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ret <3 x i32> %3
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}
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define void @masked_store4_v3(<3 x i32>, i32 addrspace(1)*, <3 x i1>) {
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entry:
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%3 = bitcast i32 addrspace(1)* %1 to <3 x i32> addrspace(1)*
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call void @llvm.masked.store.v3i32.p1v3i32(<3 x i32> %0, <3 x i32> addrspace(1)* %3, i32 4, <3 x i1> %2)
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ret void
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}
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define void @local_load_v3i1(i32 addrspace(1)* %out, i32 addrspace(1)* %in, <3 x i1>* %predicate_ptr) nounwind {
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; CHECK-LABEL: local_load_v3i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pushq %rbp
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; CHECK-NEXT: pushq %r15
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; CHECK-NEXT: pushq %r14
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; CHECK-NEXT: pushq %rbx
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; CHECK-NEXT: pushq %rax
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; CHECK-NEXT: movq %rdi, %r14
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; CHECK-NEXT: movzbl (%rdx), %ebp
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; CHECK-NEXT: movl %ebp, %eax
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; CHECK-NEXT: shrl %eax
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; CHECK-NEXT: andl $1, %eax
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; CHECK-NEXT: movl %ebp, %ecx
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; CHECK-NEXT: andl $1, %ecx
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; CHECK-NEXT: movd %ecx, %xmm0
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; CHECK-NEXT: pinsrd $1, %eax, %xmm0
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; CHECK-NEXT: shrl $2, %ebp
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; CHECK-NEXT: andl $1, %ebp
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; CHECK-NEXT: pinsrd $2, %ebp, %xmm0
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; CHECK-NEXT: movd %xmm0, %ebx
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; CHECK-NEXT: pextrd $1, %xmm0, %r15d
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; CHECK-NEXT: movq %rsi, %rdi
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; CHECK-NEXT: movl %ebx, %esi
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; CHECK-NEXT: movl %r15d, %edx
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; CHECK-NEXT: movl %ebp, %ecx
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; CHECK-NEXT: callq masked_load_v3
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; CHECK-NEXT: movq %r14, %rdi
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; CHECK-NEXT: movl %ebx, %esi
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; CHECK-NEXT: movl %r15d, %edx
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; CHECK-NEXT: movl %ebp, %ecx
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; CHECK-NEXT: callq masked_store4_v3
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; CHECK-NEXT: addq $8, %rsp
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; CHECK-NEXT: popq %rbx
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; CHECK-NEXT: popq %r14
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; CHECK-NEXT: popq %r15
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; CHECK-NEXT: popq %rbp
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; CHECK-NEXT: retq
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%predicate = load <3 x i1>, <3 x i1>* %predicate_ptr
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%load1 = call <3 x i32> @masked_load_v3(i32 addrspace(1)* %in, <3 x i1> %predicate)
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call void @masked_store4_v3(<3 x i32> %load1, i32 addrspace(1)* %out, <3 x i1> %predicate)
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ret void
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}
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@ -12,7 +12,7 @@ define void @update(<3 x i16>* %dst, <3 x i16>* %src, i32 %n) nounwind {
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; CHECK-NEXT: pushl %ebp
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; CHECK-NEXT: movl %esp, %ebp
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; CHECK-NEXT: andl $-8, %esp
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; CHECK-NEXT: subl $40, %esp
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; CHECK-NEXT: subl $32, %esp
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; CHECK-NEXT: movl {{\.LCPI.*}}, %eax
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; CHECK-NEXT: movdqa {{.*#+}} xmm1 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
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; CHECK-NEXT: pcmpeqd %xmm0, %xmm0
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@ -26,9 +26,7 @@ define void @update(<3 x i16>* %dst, <3 x i16>* %src, i32 %n) nounwind {
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: movl 12(%ebp), %edx
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; CHECK-NEXT: movl 8(%ebp), %ecx
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; CHECK-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero
|
||||
; CHECK-NEXT: pmovzxwd {{.*#+}} xmm2 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero
|
||||
; CHECK-NEXT: pinsrd $2, 4(%edx,%eax,8), %xmm2
|
||||
; CHECK-NEXT: pmovzxwd {{.*#+}} xmm2 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
|
||||
; CHECK-NEXT: psubd %xmm0, %xmm2
|
||||
; CHECK-NEXT: pextrw $4, %xmm2, 4(%ecx,%eax,8)
|
||||
; CHECK-NEXT: pshufb %xmm1, %xmm2
|
||||
|
|
|
|||
|
|
@ -21,9 +21,8 @@ define void @convert(<7 x i32>* %dst, <14 x i16>* %src) nounwind {
|
|||
; CHECK-NEXT: movdqa 16(%edx,%eax), %xmm2
|
||||
; CHECK-NEXT: psubw %xmm0, %xmm1
|
||||
; CHECK-NEXT: psubw %xmm0, %xmm2
|
||||
; CHECK-NEXT: movd %xmm2, 16(%ecx,%eax)
|
||||
; CHECK-NEXT: pextrd $1, %xmm2, 20(%ecx,%eax)
|
||||
; CHECK-NEXT: pextrd $2, %xmm2, 24(%ecx,%eax)
|
||||
; CHECK-NEXT: movq %xmm2, 16(%ecx,%eax)
|
||||
; CHECK-NEXT: movdqa %xmm1, (%ecx,%eax)
|
||||
; CHECK-NEXT: incl (%esp)
|
||||
; CHECK-NEXT: cmpl $3, (%esp)
|
||||
|
|
|
|||
|
|
@ -11,8 +11,7 @@ define void @convert(<12 x i8>* %dst.addr, <3 x i32> %src) nounwind {
|
|||
; X86-NEXT: pcmpeqd %xmm1, %xmm1
|
||||
; X86-NEXT: psubd %xmm1, %xmm0
|
||||
; X86-NEXT: pextrd $2, %xmm0, 8(%eax)
|
||||
; X86-NEXT: pextrd $1, %xmm0, 4(%eax)
|
||||
; X86-NEXT: movd %xmm0, (%eax)
|
||||
; X86-NEXT: movq %xmm0, (%eax)
|
||||
; X86-NEXT: retl
|
||||
;
|
||||
; X64-LABEL: convert:
|
||||
|
|
|
|||
|
|
@ -15,8 +15,7 @@ define void @add3i32(%i32vec3* sret %ret, %i32vec3* %ap, %i32vec3* %bp) {
|
|||
; X86-NEXT: movdqa (%edx), %xmm0
|
||||
; X86-NEXT: paddd (%ecx), %xmm0
|
||||
; X86-NEXT: pextrd $2, %xmm0, 8(%eax)
|
||||
; X86-NEXT: pextrd $1, %xmm0, 4(%eax)
|
||||
; X86-NEXT: movd %xmm0, (%eax)
|
||||
; X86-NEXT: movq %xmm0, (%eax)
|
||||
; X86-NEXT: retl $4
|
||||
;
|
||||
; X64-LABEL: add3i32:
|
||||
|
|
@ -40,16 +39,13 @@ define void @add3i32_2(%i32vec3* sret %ret, %i32vec3* %ap, %i32vec3* %bp) {
|
|||
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
|
||||
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
|
||||
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
|
||||
; X86-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
|
||||
; X86-NEXT: pinsrd $1, 4(%edx), %xmm0
|
||||
; X86-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
|
||||
; X86-NEXT: pinsrd $2, 8(%edx), %xmm0
|
||||
; X86-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
|
||||
; X86-NEXT: pinsrd $1, 4(%ecx), %xmm1
|
||||
; X86-NEXT: movq {{.*#+}} xmm1 = mem[0],zero
|
||||
; X86-NEXT: pinsrd $2, 8(%ecx), %xmm1
|
||||
; X86-NEXT: paddd %xmm0, %xmm1
|
||||
; X86-NEXT: pextrd $1, %xmm1, 4(%eax)
|
||||
; X86-NEXT: movq %xmm1, (%eax)
|
||||
; X86-NEXT: pextrd $2, %xmm1, 8(%eax)
|
||||
; X86-NEXT: movd %xmm1, (%eax)
|
||||
; X86-NEXT: retl $4
|
||||
;
|
||||
; X64-LABEL: add3i32_2:
|
||||
|
|
@ -81,9 +77,8 @@ define void @add7i32(%i32vec7* sret %ret, %i32vec7* %ap, %i32vec7* %bp) {
|
|||
; X86-NEXT: movdqa 16(%edx), %xmm1
|
||||
; X86-NEXT: paddd (%ecx), %xmm0
|
||||
; X86-NEXT: paddd 16(%ecx), %xmm1
|
||||
; X86-NEXT: movd %xmm1, 16(%eax)
|
||||
; X86-NEXT: pextrd $1, %xmm1, 20(%eax)
|
||||
; X86-NEXT: pextrd $2, %xmm1, 24(%eax)
|
||||
; X86-NEXT: movq %xmm1, 16(%eax)
|
||||
; X86-NEXT: movdqa %xmm0, (%eax)
|
||||
; X86-NEXT: retl $4
|
||||
;
|
||||
|
|
@ -151,16 +146,12 @@ define void @add3i16(%i16vec3* nocapture sret %ret, %i16vec3* %ap, %i16vec3* %bp
|
|||
; X86-NEXT: pushl %ebp
|
||||
; X86-NEXT: movl %esp, %ebp
|
||||
; X86-NEXT: andl $-8, %esp
|
||||
; X86-NEXT: subl $24, %esp
|
||||
; X86-NEXT: subl $8, %esp
|
||||
; X86-NEXT: movl 8(%ebp), %eax
|
||||
; X86-NEXT: movl 16(%ebp), %ecx
|
||||
; X86-NEXT: movl 12(%ebp), %edx
|
||||
; X86-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
|
||||
; X86-NEXT: pmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
|
||||
; X86-NEXT: pinsrd $2, 4(%edx), %xmm0
|
||||
; X86-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
|
||||
; X86-NEXT: pmovzxwd {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero
|
||||
; X86-NEXT: pinsrd $2, 4(%ecx), %xmm1
|
||||
; X86-NEXT: pmovzxwd {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
|
||||
; X86-NEXT: pmovzxwd {{.*#+}} xmm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
|
||||
; X86-NEXT: paddd %xmm0, %xmm1
|
||||
; X86-NEXT: pextrw $4, %xmm1, 4(%eax)
|
||||
; X86-NEXT: pshufb {{.*#+}} xmm1 = xmm1[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
|
||||
|
|
@ -225,8 +216,7 @@ define void @add12i16(%i16vec12* nocapture sret %ret, %i16vec12* %ap, %i16vec12*
|
|||
; X86-NEXT: movdqa 16(%edx), %xmm1
|
||||
; X86-NEXT: paddw (%ecx), %xmm0
|
||||
; X86-NEXT: paddw 16(%ecx), %xmm1
|
||||
; X86-NEXT: movd %xmm1, 16(%eax)
|
||||
; X86-NEXT: pextrd $1, %xmm1, 20(%eax)
|
||||
; X86-NEXT: movq %xmm1, 16(%eax)
|
||||
; X86-NEXT: movdqa %xmm0, (%eax)
|
||||
; X86-NEXT: retl $4
|
||||
;
|
||||
|
|
@ -331,11 +321,10 @@ define void @add31i8(%i8vec31* nocapture sret %ret, %i8vec31* %ap, %i8vec31* %bp
|
|||
; X86-NEXT: movdqa 16(%edx), %xmm1
|
||||
; X86-NEXT: paddb (%ecx), %xmm0
|
||||
; X86-NEXT: paddb 16(%ecx), %xmm1
|
||||
; X86-NEXT: movd %xmm1, 16(%eax)
|
||||
; X86-NEXT: pextrd $1, %xmm1, 20(%eax)
|
||||
; X86-NEXT: pextrd $2, %xmm1, 24(%eax)
|
||||
; X86-NEXT: pextrw $6, %xmm1, 28(%eax)
|
||||
; X86-NEXT: pextrb $14, %xmm1, 30(%eax)
|
||||
; X86-NEXT: movq %xmm1, 16(%eax)
|
||||
; X86-NEXT: movdqa %xmm0, (%eax)
|
||||
; X86-NEXT: retl $4
|
||||
;
|
||||
|
|
|
|||
Loading…
Reference in New Issue