From b16081ce8cbcffb99d9359764db2616f71bb2cdb Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Thu, 28 Jul 2011 21:38:51 +0000 Subject: [PATCH] Handle REG_SEQUENCE with implicitly defined operands. Code like that would only be produced by bugpoint, but we should still handle it correctly. When a register is defined by a REG_SEQUENCE of undefs, the register itself is undef. Previously, we would create a register with uses but no defs. Fixes part of PR10520. llvm-svn: 136401 --- llvm/lib/CodeGen/ProcessImplicitDefs.cpp | 6 ++++++ llvm/test/CodeGen/ARM/crash.ll | 21 +++++++++++++++++++++ 2 files changed, 27 insertions(+) diff --git a/llvm/lib/CodeGen/ProcessImplicitDefs.cpp b/llvm/lib/CodeGen/ProcessImplicitDefs.cpp index c04d65637c94..b1d8c9760225 100644 --- a/llvm/lib/CodeGen/ProcessImplicitDefs.cpp +++ b/llvm/lib/CodeGen/ProcessImplicitDefs.cpp @@ -125,8 +125,14 @@ bool ProcessImplicitDefs::runOnMachineFunction(MachineFunction &fn) { LiveVariables::VarInfo& vi = LV->getVarInfo(MO.getReg()); vi.removeKill(MI); } + unsigned Reg = MI->getOperand(0).getReg(); MI->eraseFromParent(); Changed = true; + + // A REG_SEQUENCE may have been expanded into partial definitions. + // If this was the last one, mark Reg as implicitly defined. + if (TargetRegisterInfo::isVirtualRegister(Reg) && MRI->def_empty(Reg)) + ImpDefRegs.insert(Reg); continue; } } diff --git a/llvm/test/CodeGen/ARM/crash.ll b/llvm/test/CodeGen/ARM/crash.ll index 4b6876df4a03..5ecfe15511b9 100644 --- a/llvm/test/CodeGen/ARM/crash.ll +++ b/llvm/test/CodeGen/ARM/crash.ll @@ -27,3 +27,24 @@ bb3: exit: ret void } + +; PR10520 - REG_SEQUENCE with implicit-def operands. +define arm_aapcs_vfpcc void @foo() nounwind align 2 { +bb: + %tmp = shufflevector <2 x i64> undef, <2 x i64> undef, <1 x i32> + %tmp8 = bitcast <1 x i64> %tmp to <2 x float> + %tmp9 = shufflevector <2 x float> %tmp8, <2 x float> %tmp8, <4 x i32> + %tmp10 = fmul <4 x float> undef, %tmp9 + %tmp11 = fadd <4 x float> %tmp10, undef + %tmp12 = fadd <4 x float> undef, %tmp11 + %tmp13 = bitcast <4 x float> %tmp12 to i128 + %tmp14 = bitcast i128 %tmp13 to <4 x float> + %tmp15 = bitcast <4 x float> %tmp14 to i128 + %tmp16 = bitcast i128 %tmp15 to <4 x float> + %tmp17 = bitcast <4 x float> %tmp16 to i128 + %tmp18 = bitcast i128 %tmp17 to <4 x float> + %tmp19 = bitcast <4 x float> %tmp18 to i128 + %tmp20 = bitcast i128 %tmp19 to <4 x float> + store <4 x float> %tmp20, <4 x float>* undef, align 16 + ret void +}