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Handle REG_SEQUENCE with implicitly defined operands. 

Code like that would only be produced by bugpoint, but we should still
handle it correctly.

When a register is defined by a REG_SEQUENCE of undefs, the register
itself is undef. Previously, we would create a register with uses but no
defs.

Fixes part of PR10520.

llvm-svn: 136401
This commit is contained in:
Jakob Stoklund Olesen 2011-07-28 21:38:51 +00:00
parent 7f45559e86
commit b16081ce8c
2 changed files with 27 additions and 0 deletions
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6
llvm/lib/CodeGen/ProcessImplicitDefs.cpp
View File

@ -125,8 +125,14 @@ bool ProcessImplicitDefs::runOnMachineFunction(MachineFunction &fn) {
LiveVariables::VarInfo& vi = LV->getVarInfo(MO.getReg());
vi.removeKill(MI);
}
unsigned Reg = MI->getOperand(0).getReg();
MI->eraseFromParent();
Changed = true;
// A REG_SEQUENCE may have been expanded into partial definitions.
// If this was the last one, mark Reg as implicitly defined.
if (TargetRegisterInfo::isVirtualRegister(Reg) && MRI->def_empty(Reg))
ImpDefRegs.insert(Reg);
continue;
}
}

21
llvm/test/CodeGen/ARM/crash.ll
View File

@ -27,3 +27,24 @@ bb3:
exit:
ret void
}
; PR10520 - REG_SEQUENCE with implicit-def operands.
define arm_aapcs_vfpcc void @foo() nounwind align 2 {
bb:
%tmp = shufflevector <2 x i64> undef, <2 x i64> undef, <1 x i32> <i32 1>
%tmp8 = bitcast <1 x i64> %tmp to <2 x float>
%tmp9 = shufflevector <2 x float> %tmp8, <2 x float> %tmp8, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
%tmp10 = fmul <4 x float> undef, %tmp9
%tmp11 = fadd <4 x float> %tmp10, undef
%tmp12 = fadd <4 x float> undef, %tmp11
%tmp13 = bitcast <4 x float> %tmp12 to i128
%tmp14 = bitcast i128 %tmp13 to <4 x float>
%tmp15 = bitcast <4 x float> %tmp14 to i128
%tmp16 = bitcast i128 %tmp15 to <4 x float>
%tmp17 = bitcast <4 x float> %tmp16 to i128
%tmp18 = bitcast i128 %tmp17 to <4 x float>
%tmp19 = bitcast <4 x float> %tmp18 to i128
%tmp20 = bitcast i128 %tmp19 to <4 x float>
store <4 x float> %tmp20, <4 x float>* undef, align 16
ret void
}