diff --git a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
index ec2b145f9ac3..57090b98e43e 100644
--- a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -81,11 +81,17 @@ static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
   return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
 }
 
+static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {
+  assert(0 && "Not implemented");
+}
+
 SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
   switch (Op.getOpcode()) {
   default:
     assert(0 && "Should not custom lower this!");
     abort();
+  case ISD::FORMAL_ARGUMENTS:
+    return LowerFORMAL_ARGUMENTS(Op, DAG);
   case ISD::RET:
     return LowerRET(Op, DAG);
   }
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td
index 318c230586be..f7069275333e 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.td
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.td
@@ -42,6 +42,8 @@ def ADJCALLSTACKDOWN : InstARM<(ops i32imm:$amt),
                                "!ADJCALLSTACKDOWN $amt",
                                [(callseq_start imm:$amt)]>;
 
+def BX: InstARM<(ops), "bx", [(retflag)]>;
+
 def ldr   : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
                      "ldr $dst, [$addr]",
                      [(set IntRegs:$dst, (load IntRegs:$addr))]>;
@@ -50,5 +52,8 @@ def str  : InstARM<(ops IntRegs:$src, IntRegs:$addr),
                     "str $src, [$addr]",
                     [(store IntRegs:$src, IntRegs:$addr)]>;
 
-def mov   : InstARM<(ops IntRegs:$dst, IntRegs:$b),
-                    "mov $dst, $b", []>;
+def movrr   : InstARM<(ops IntRegs:$dst, IntRegs:$src),
+                       "mov $dst, $src", []>;
+
+def movri   : InstARM<(ops IntRegs:$dst, i32imm:$src),
+                       "mov $dst, $src", [(set IntRegs:$dst, imm:$src)]>;
diff --git a/llvm/lib/Target/ARM/ARMRegisterInfo.cpp b/llvm/lib/Target/ARM/ARMRegisterInfo.cpp
index e56eef47241f..18e273134c52 100644
--- a/llvm/lib/Target/ARM/ARMRegisterInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMRegisterInfo.cpp
@@ -49,7 +49,7 @@ void ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
                                      unsigned DestReg, unsigned SrcReg,
                                      const TargetRegisterClass *RC) const {
   assert (RC == ARM::IntRegsRegisterClass);
-  BuildMI(MBB, I, ARM::mov, 1, DestReg).addReg(SrcReg);
+  BuildMI(MBB, I, ARM::movrr, 1, DestReg).addReg(SrcReg);
 }
 
 MachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr* MI,