[GlobalISel] Add Selected MachineFunction property.

Selected: the InstructionSelect pass ran and all pre-isel generic
instructions have been eliminated; i.e., all instructions are now
target-specific or non-pre-isel generic instructions (e.g., COPY).

Since only pre-isel generic instructions can have generic virtual register
operands, this also means that all generic virtual registers have been
constrained to virtual registers (assigned to register classes) and that
all sizes attached to them have been eliminated.

This lets us enforce certain invariants across passes.
This property is GlobalISel-specific, but is always available.

llvm-svn: 277482

llvm/include/llvm/CodeGen/MIRYamlMapping.h

@@ -387,6 +387,7 @@ struct MachineFunction {
   // GISel MachineFunctionProperties.
   bool Legalized = false;
   bool RegBankSelected = false;
+  bool Selected = false;
   // Register information
   bool IsSSA = false;
   bool TracksRegLiveness = false;
@@ -413,6 +414,7 @@ template <> struct MappingTraits<MachineFunction> {
     YamlIO.mapOptional("allVRegsAllocated", MF.AllVRegsAllocated);
     YamlIO.mapOptional("legalized", MF.Legalized);
     YamlIO.mapOptional("regBankSelected", MF.RegBankSelected);
+    YamlIO.mapOptional("selected", MF.Selected);
     YamlIO.mapOptional("isSSA", MF.IsSSA);
     YamlIO.mapOptional("tracksRegLiveness", MF.TracksRegLiveness);
     YamlIO.mapOptional("tracksSubRegLiveness", MF.TracksSubRegLiveness);

llvm/include/llvm/CodeGen/MachineFunction.h

@@ -124,12 +124,20 @@ public:
   //   - legal pre-isel generic instructions.
   // RegBankSelected: In GlobalISel: the RegBankSelect pass ran and all generic
   //  virtual registers have been assigned to a register bank.
+  // Selected: In GlobalISel: the InstructionSelect pass ran and all pre-isel
+  //  generic instructions have been eliminated; i.e., all instructions are now
+  //  target-specific or non-pre-isel generic instructions (e.g., COPY).
+  //  Since only pre-isel generic instructions can have generic virtual register
+  //  operands, this also means that all generic virtual registers have been
+  //  constrained to virtual registers (assigned to register classes) and that
+  //  all sizes attached to them have been eliminated.
   enum class Property : unsigned {
     IsSSA,
     TracksLiveness,
     AllVRegsAllocated,
     Legalized,
     RegBankSelected,
+    Selected,
     LastProperty,
   };
 

llvm/lib/CodeGen/MIRParser/MIRParser.cpp

@@ -298,6 +298,8 @@ bool MIRParserImpl::initializeMachineFunction(MachineFunction &MF) {
   if (YamlMF.RegBankSelected)
     MF.getProperties().set(
         MachineFunctionProperties::Property::RegBankSelected);
+  if (YamlMF.Selected)
+    MF.getProperties().set(MachineFunctionProperties::Property::Selected);
 
   PerFunctionMIParsingState PFS(MF, SM, IRSlots);
   if (initializeRegisterInfo(PFS, YamlMF))

llvm/lib/CodeGen/MIRPrinter.cpp

@@ -182,6 +182,8 @@ void MIRPrinter::print(const MachineFunction &MF) {
       MachineFunctionProperties::Property::Legalized);
   YamlMF.RegBankSelected = MF.getProperties().hasProperty(
       MachineFunctionProperties::Property::RegBankSelected);
+  YamlMF.Selected = MF.getProperties().hasProperty(
+      MachineFunctionProperties::Property::Selected);
 
   convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
   ModuleSlotTracker MST(MF.getFunction()->getParent());

llvm/lib/CodeGen/MachineFunction.cpp

@@ -82,6 +82,9 @@ void MachineFunctionProperties::print(raw_ostream &ROS, bool OnlySet) const {
       case Property::RegBankSelected:
         ROS << (HasProperty ? "" : "not ") << "RegBank-selected";
         break;
+      case Property::Selected:
+        ROS << (HasProperty ? "" : "not ") << "selected";
+        break;
       default:
         break;
     }

llvm/test/CodeGen/MIR/Generic/global-isel-properties.mir

@@ -21,6 +21,7 @@
 # CHECK-LABEL: name: test_defaults
 # CHECK:      legalized: false
 # CHECK-NEXT: regBankSelected: false
+# CHECK-NEXT: selected: false
 name:            test_defaults
 body: |
   bb.0:
@@ -29,9 +30,11 @@ body: |
 # CHECK-LABEL: name: test
 # CHECK:      legalized: true
 # CHECK-NEXT: regBankSelected: true
+# CHECK-NEXT: selected: true
 name: test
 legalized: true
 regBankSelected: true
+selected: true
 body: |
   bb.0:
 ...