forked from OSchip/llvm-project
parent
871784ba88
commit
b106b60456
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@ -186,50 +186,71 @@ bool
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SystemZInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI) const {
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if (CSI.empty())
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return false;
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DebugLoc DL = DebugLoc::getUnknownLoc();
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if (MI != MBB.end()) DL = MI->getDebugLoc();
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MachineFunction &MF = *MBB.getParent();
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SystemZMachineFunctionInfo *MFI = MF.getInfo<SystemZMachineFunctionInfo>();
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MFI->setCalleeSavedFrameSize(CSI.size() * 8);
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unsigned CalleeFrameSize = 0;
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// Scan the callee-saved and find the bounds of register spill area.
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unsigned LowReg = 0, HighReg = 0, StartOffset = -1U, EndOffset = 0;
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for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
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unsigned Reg = CSI[i].getReg();
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unsigned Offset = RegSpillOffsets[Reg];
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if (StartOffset > Offset) {
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LowReg = Reg; StartOffset = Offset;
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}
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if (EndOffset < Offset) {
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HighReg = Reg; EndOffset = RegSpillOffsets[Reg];
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const TargetRegisterClass *RegClass = CSI[i].getRegClass();
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if (RegClass != &SystemZ::FP64RegClass) {
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unsigned Offset = RegSpillOffsets[Reg];
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CalleeFrameSize += 8;
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if (StartOffset > Offset) {
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LowReg = Reg; StartOffset = Offset;
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}
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if (EndOffset < Offset) {
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HighReg = Reg; EndOffset = RegSpillOffsets[Reg];
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}
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}
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}
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// Save information for epilogue inserter.
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MFI->setCalleeSavedFrameSize(CalleeFrameSize);
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MFI->setLowReg(LowReg); MFI->setHighReg(HighReg);
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// Build a store instruction. Use STORE MULTIPLE instruction if there are many
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// registers to store, otherwise - just STORE.
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MachineInstrBuilder MIB =
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BuildMI(MBB, MI, DL, get((LowReg == HighReg ?
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SystemZ::MOV64mr : SystemZ::MOV64mrm)));
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// Save GPRs
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if (StartOffset) {
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// Build a store instruction. Use STORE MULTIPLE instruction if there are many
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// registers to store, otherwise - just STORE.
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MachineInstrBuilder MIB =
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BuildMI(MBB, MI, DL, get((LowReg == HighReg ?
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SystemZ::MOV64mr : SystemZ::MOV64mrm)));
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// Add store operands.
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MIB.addReg(SystemZ::R15D).addImm(StartOffset);
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if (LowReg == HighReg)
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MIB.addReg(0);
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MIB.addReg(LowReg, RegState::Kill);
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if (LowReg != HighReg)
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MIB.addReg(HighReg, RegState::Kill);
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// Add store operands.
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MIB.addReg(SystemZ::R15D).addImm(StartOffset);
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if (LowReg == HighReg)
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MIB.addReg(0);
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MIB.addReg(LowReg, RegState::Kill);
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if (LowReg != HighReg)
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MIB.addReg(HighReg, RegState::Kill);
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// Do a second scan adding regs as being killed by instruction
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// Do a second scan adding regs as being killed by instruction
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for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
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unsigned Reg = CSI[i].getReg();
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// Add the callee-saved register as live-in. It's killed at the spill.
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MBB.addLiveIn(Reg);
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if (Reg != LowReg && Reg != HighReg)
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MIB.addReg(Reg, RegState::ImplicitKill);
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}
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}
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// Save FPRs
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for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
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unsigned Reg = CSI[i].getReg();
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// Add the callee-saved register as live-in. It's killed at the spill.
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MBB.addLiveIn(Reg);
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if (Reg != LowReg && Reg != HighReg)
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MIB.addReg(Reg, RegState::ImplicitKill);
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const TargetRegisterClass *RegClass = CSI[i].getRegClass();
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if (RegClass == &SystemZ::FP64RegClass) {
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MBB.addLiveIn(Reg);
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storeRegToStackSlot(MBB, MI, Reg, true, CSI[i].getFrameIdx(), RegClass);
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}
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}
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return true;
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@ -249,29 +270,40 @@ SystemZInstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
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const TargetRegisterInfo *RegInfo= MF.getTarget().getRegisterInfo();
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SystemZMachineFunctionInfo *MFI = MF.getInfo<SystemZMachineFunctionInfo>();
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// Restore FP registers
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for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
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unsigned Reg = CSI[i].getReg();
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const TargetRegisterClass *RegClass = CSI[i].getRegClass();
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if (RegClass == &SystemZ::FP64RegClass)
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loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RegClass);
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}
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// Restore GP registers
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unsigned LowReg = MFI->getLowReg(), HighReg = MFI->getHighReg();
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unsigned StartOffset = RegSpillOffsets[LowReg];
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// Build a load instruction. Use LOAD MULTIPLE instruction if there are many
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// registers to load, otherwise - just LOAD.
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MachineInstrBuilder MIB =
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BuildMI(MBB, MI, DL, get((LowReg == HighReg ?
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SystemZ::MOV64rm : SystemZ::MOV64rmm)));
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// Add store operands.
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MIB.addReg(LowReg, RegState::Define);
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if (LowReg != HighReg)
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MIB.addReg(HighReg, RegState::Define);
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if (StartOffset) {
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// Build a load instruction. Use LOAD MULTIPLE instruction if there are many
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// registers to load, otherwise - just LOAD.
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MachineInstrBuilder MIB =
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BuildMI(MBB, MI, DL, get((LowReg == HighReg ?
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SystemZ::MOV64rm : SystemZ::MOV64rmm)));
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// Add store operands.
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MIB.addReg(LowReg, RegState::Define);
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if (LowReg != HighReg)
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MIB.addReg(HighReg, RegState::Define);
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MIB.addReg((RegInfo->hasFP(MF) ? SystemZ::R11D : SystemZ::R15D));
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MIB.addImm(StartOffset);
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if (LowReg == HighReg)
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MIB.addReg(0);
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MIB.addReg((RegInfo->hasFP(MF) ? SystemZ::R11D : SystemZ::R15D));
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MIB.addImm(StartOffset);
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if (LowReg == HighReg)
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MIB.addReg(0);
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// Do a second scan adding regs as being defined by instruction
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for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
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unsigned Reg = CSI[i].getReg();
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if (Reg != LowReg && Reg != HighReg)
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MIB.addReg(Reg, RegState::ImplicitDefine);
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// Do a second scan adding regs as being defined by instruction
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for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
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unsigned Reg = CSI[i].getReg();
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if (Reg != LowReg && Reg != HighReg)
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MIB.addReg(Reg, RegState::ImplicitDefine);
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}
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}
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return true;
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@ -156,7 +156,8 @@ let isBranch = 1, isTerminator = 1 in {
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let isCall = 1 in
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// All calls clobber the non-callee saved registers. Uses for argument
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// registers are added manually.
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let Defs = [R0D, R1D, R2D, R3D, R4D, R5D, R14D] in {
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let Defs = [R0D, R1D, R2D, R3D, R4D, R5D, R14D,
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F0L, F1L, F2L, F3L, F4L, F5L, F6L, F7L] in {
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def CALLi : Pseudo<(outs), (ins imm_pcrel:$dst, variable_ops),
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"brasl\t%r14, $dst", [(SystemZcall imm:$dst)]>;
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def CALLr : Pseudo<(outs), (ins ADDR64:$dst, variable_ops),
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@ -39,7 +39,8 @@ SystemZRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
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SystemZ::R6D, SystemZ::R7D, SystemZ::R8D, SystemZ::R9D,
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SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D,
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SystemZ::R14D, SystemZ::R15D,
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SystemZ::F1L, SystemZ::F3L, SystemZ::F5L, SystemZ::F7L,
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SystemZ::F8L, SystemZ::F9L, SystemZ::F10L, SystemZ::F11L,
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SystemZ::F12L, SystemZ::F13L, SystemZ::F14L, SystemZ::F15L,
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0
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};
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@ -55,6 +56,8 @@ SystemZRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
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&SystemZ::GR64RegClass, &SystemZ::GR64RegClass,
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&SystemZ::GR64RegClass, &SystemZ::GR64RegClass,
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&SystemZ::FP64RegClass, &SystemZ::FP64RegClass,
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&SystemZ::FP64RegClass, &SystemZ::FP64RegClass,
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&SystemZ::FP64RegClass, &SystemZ::FP64RegClass,
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&SystemZ::FP64RegClass, &SystemZ::FP64RegClass, 0
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};
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return CalleeSavedRegClasses;
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@ -142,18 +145,33 @@ SystemZRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
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// Determine whether R15/R14 will ever be clobbered inside the function. And
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// if yes - mark it as 'callee' saved.
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MachineFrameInfo *FFI = MF.getFrameInfo();
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MachineRegisterInfo &MRI = MF.getRegInfo();
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// Check whether high FPRs are ever used, if yes - we need to save R15 as
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// well.
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static const unsigned HighFPRs[] = {
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SystemZ::F8L, SystemZ::F9L, SystemZ::F10L, SystemZ::F11L,
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SystemZ::F12L, SystemZ::F13L, SystemZ::F14L, SystemZ::F15L,
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SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S,
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SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S,
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};
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bool HighFPRsUsed = false;
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for (unsigned i = 0, e = array_lengthof(HighFPRs); i != e; ++i)
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HighFPRsUsed |= MRI.isPhysRegUsed(HighFPRs[i]);
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if (FFI->hasCalls())
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/* FIXME: function is varargs */
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/* FIXME: function grabs RA */
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/* FIXME: function calls eh_return */
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MF.getRegInfo().setPhysRegUsed(SystemZ::R14D);
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MRI.setPhysRegUsed(SystemZ::R14D);
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if (FFI->hasCalls() ||
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if (HighFPRsUsed ||
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FFI->hasCalls() ||
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FFI->getObjectIndexEnd() != 0 || // Contains automatic variables
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FFI->hasVarSizedObjects() // Function calls dynamic alloca's
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/* FIXME: function is varargs */)
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MF.getRegInfo().setPhysRegUsed(SystemZ::R15D);
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MRI.setPhysRegUsed(SystemZ::R15D);
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}
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/// emitSPUpdate - Emit a series of instructions to increment / decrement the
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