forked from OSchip/llvm-project
[llvm-objcopy] Fix sparc target endianness
Summary: AFAIK, the "sparc" target is big endian and the target for 32-bit little-endian SPARC is denoted as "sparcel". This patch fixes the endianness of "sparc" target and adds "sparcel" target for 32-bit little-endian SPARC. Reviewers: espindola, alexshap, rupprecht, jhenderson Reviewed By: jhenderson Subscribers: jyknight, emaste, arichardson, fedor.sergeev, jakehehrlich, MaskRay, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63251 llvm-svn: 363336
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@ -25,7 +25,10 @@
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# RUN: llvm-readobj --file-headers %t.rv64.o | FileCheck %s --check-prefixes=CHECK,LE,RISCV64,64
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# RUN: llvm-objcopy -I binary -B sparc %t.txt %t.sparc.o
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# RUN: llvm-readobj --file-headers %t.sparc.o | FileCheck %s --check-prefixes=CHECK,LE,SPARC,32
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# RUN: llvm-readobj --file-headers %t.sparc.o | FileCheck %s --check-prefixes=CHECK,BE,SPARC,32
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# RUN: llvm-objcopy -I binary -B sparcel %t.txt %t.sparcel.o
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# RUN: llvm-readobj --file-headers %t.sparcel.o | FileCheck %s --check-prefixes=CHECK,LE,SPARCEL,32
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# RUN: llvm-objcopy -I binary -B x86-64 %t.txt %t.x86-64.o
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# RUN: llvm-readobj --file-headers %t.x86-64.o | FileCheck %s --check-prefixes=CHECK,LE,X86-64,64
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@ -41,6 +44,7 @@
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# RISCV64-SAME: riscv{{$}}
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# PPC-SAME: ppc64
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# SPARC-SAME: sparc
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# SPARCEL-SAME: sparc
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# X86-64-SAME: x86-64
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# AARCH64-NEXT: Arch: aarch64
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@ -50,7 +54,8 @@
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# PPC-NEXT: Arch: powerpc64le
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# RISCV32-NEXT: Arch: riscv32
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# RISCV64-NEXT: Arch: riscv64
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# SPARC-NEXT: Arch: sparcel
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# SPARC-NEXT: Arch: sparc{{$}}
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# SPARCEL-NEXT: Arch: sparcel
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# X86-64-NEXT: Arch: x86_64
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# 32-NEXT: AddressSize: 32bit
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@ -77,6 +82,7 @@
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# RISCV32-NEXT: Machine: EM_RISCV (0xF3)
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# RISCV64-NEXT: Machine: EM_RISCV (0xF3)
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# SPARC-NEXT: Machine: EM_SPARC (0x2)
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# SPARCEL-NEXT: Machine: EM_SPARC (0x2)
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# X86-64-NEXT: Machine: EM_X86_64 (0x3E)
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# CHECK-NEXT: Version: 1
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# CHECK-NEXT: Entry: 0x0
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@ -263,7 +263,8 @@ static const StringMap<MachineInfo> ArchMap{
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{"powerpc:common64", {ELF::EM_PPC64, true, true}},
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{"riscv:rv32", {ELF::EM_RISCV, false, true}},
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{"riscv:rv64", {ELF::EM_RISCV, true, true}},
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{"sparc", {ELF::EM_SPARC, false, true}},
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{"sparc", {ELF::EM_SPARC, false, false}},
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{"sparcel", {ELF::EM_SPARC, false, true}},
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{"x86-64", {ELF::EM_X86_64, true, true}},
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};
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