forked from OSchip/llvm-project
parent
4583355a78
commit
b1021395b8
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@ -1630,23 +1630,23 @@ defm SBCS : AI1_adde_sube_s_irs<0b0110, "sbcs",
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BinOpFrag<(sube_live_carry node:$LHS, node:$RHS) >>;
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def RSBri : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
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IIC_iALUi, "rsb", "\t$dst, $a, $b",
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[(set GPR:$dst, (sub so_imm:$b, GPR:$a))]> {
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IIC_iALUi, "rsb", "\t$dst, $a, $b",
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[(set GPR:$dst, (sub so_imm:$b, GPR:$a))]> {
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let Inst{25} = 1;
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}
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// The reg/reg form is only defined for the disassembler; for codegen it is
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// equivalent to SUBrr.
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def RSBrr : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm,
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IIC_iALUr, "rsb", "\t$dst, $a, $b",
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[/* For disassembly only; pattern left blank */]> {
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IIC_iALUr, "rsb", "\t$dst, $a, $b",
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[/* For disassembly only; pattern left blank */]> {
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let Inst{25} = 0;
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let Inst{11-4} = 0b00000000;
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}
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def RSBrs : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
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IIC_iALUsr, "rsb", "\t$dst, $a, $b",
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[(set GPR:$dst, (sub so_reg:$b, GPR:$a))]> {
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IIC_iALUsr, "rsb", "\t$dst, $a, $b",
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[(set GPR:$dst, (sub so_reg:$b, GPR:$a))]> {
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let Inst{25} = 0;
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}
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