forked from OSchip/llvm-project
[RISCV] Emit DWARF location expression for RVV stack objects.
VLENB is the length of a vector register in bytes. We use <vscale x 64 bits> to represent one vector register. The dwarf offset is VLENB * scalable_offset / 8. For the mask vector, it occupies one vector register. Differential Revision: https://reviews.llvm.org/D107432
This commit is contained in:
Hsiangkai Wang
parent
387927bbaf
commit
b0c7421524
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@ -20,6 +20,7 @@
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/CodeGen/TargetFrameLowering.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/IR/DebugInfoMetadata.h"
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#include "llvm/Support/ErrorHandling.h"
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#define GET_REGINFO_TARGET_DESC
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@ -320,3 +321,30 @@ RISCVRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
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return &RISCV::VRRegClass;
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return RC;
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}
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void RISCVRegisterInfo::getOffsetOpcodes(const StackOffset &Offset,
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SmallVectorImpl<uint64_t> &Ops) const {
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// VLENB is the length of a vector register in bytes. We use <vscale x 8 x i8>
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// to represent one vector register. The dwarf offset is
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// VLENB * scalable_offset / 8.
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assert(Offset.getScalable() % 8 == 0 && "Invalid frame offset");
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// Add fixed-sized offset using existing DIExpression interface.
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DIExpression::appendOffset(Ops, Offset.getFixed());
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unsigned VLENB = getDwarfRegNum(RISCV::VLENB, true);
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int64_t VLENBSized = Offset.getScalable() / 8;
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if (VLENBSized > 0) {
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Ops.push_back(dwarf::DW_OP_constu);
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Ops.push_back(VLENBSized);
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Ops.append({dwarf::DW_OP_bregx, VLENB, 0ULL});
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Ops.push_back(dwarf::DW_OP_mul);
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Ops.push_back(dwarf::DW_OP_plus);
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} else if (VLENBSized < 0) {
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Ops.push_back(dwarf::DW_OP_constu);
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Ops.push_back(-VLENBSized);
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Ops.append({dwarf::DW_OP_bregx, VLENB, 0ULL});
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Ops.push_back(dwarf::DW_OP_mul);
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Ops.push_back(dwarf::DW_OP_minus);
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}
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}
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@ -63,6 +63,9 @@ struct RISCVRegisterInfo : public RISCVGenRegisterInfo {
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const TargetRegisterClass *
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getLargestLegalSuperClass(const TargetRegisterClass *RC,
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const MachineFunction &) const override;
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void getOffsetOpcodes(const StackOffset &Offset,
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SmallVectorImpl<uint64_t> &Ops) const override;
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};
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}
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@ -480,6 +480,8 @@ let RegAltNameIndices = [ABIRegAltName] in {
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def VL : RISCVReg<0, "vl", ["vl"]>;
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def VXSAT : RISCVReg<0, "vxsat", ["vxsat"]>;
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def VXRM : RISCVReg<0, "vxrm", ["vxrm"]>;
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def VLENB : RISCVReg<0, "vlenb", ["vlenb"]>,
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DwarfRegNum<[!add(4096, SysRegVLENB.Encoding)]>;
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}
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foreach m = [1, 2, 4] in {
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@ -388,4 +388,4 @@ def : SysReg<"vxrm", 0x00A>;
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def : SysReg<"vcsr", 0x00F>;
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def : SysReg<"vl", 0xC20>;
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def : SysReg<"vtype", 0xC21>;
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def : SysReg<"vlenb", 0xC22>;
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def SysRegVLENB: SysReg<"vlenb", 0xC22>;
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@ -0,0 +1,143 @@
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# RUN: llc -march=riscv64 -mattr=+experimental-v -o %t0 -filetype=obj \
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# RUN: -start-before=prologepilog %s
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# RUN: llc -march=riscv64 -mattr=+experimental-v -o %t1 -filetype=obj \
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# RUN: -frame-pointer=all -start-before=prologepilog %s
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# RUN: llvm-dwarfdump --name="value0" %t0 | FileCheck %s --check-prefix=CHECK0-PLUS
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# RUN: llvm-dwarfdump --name="value1" %t0 | FileCheck %s --check-prefix=CHECK1-PLUS
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# RUN: llvm-dwarfdump --name="value2" %t0 | FileCheck %s --check-prefix=CHECK2-PLUS
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# RUN: llvm-dwarfdump --name="value3" %t0 | FileCheck %s --check-prefix=CHECK3-PLUS
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# RUN: llvm-dwarfdump --name="value4" %t0 | FileCheck %s --check-prefix=CHECK4-PLUS
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# RUN: llvm-dwarfdump --name="value5" %t0 | FileCheck %s --check-prefix=CHECK5-PLUS
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# RUN: llvm-dwarfdump --name="value0" %t1 | FileCheck %s --check-prefix=CHECK0-MINUS
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# RUN: llvm-dwarfdump --name="value1" %t1 | FileCheck %s --check-prefix=CHECK1-MINUS
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# RUN: llvm-dwarfdump --name="value2" %t1 | FileCheck %s --check-prefix=CHECK2-MINUS
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# RUN: llvm-dwarfdump --name="value3" %t1 | FileCheck %s --check-prefix=CHECK3-MINUS
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# RUN: llvm-dwarfdump --name="value4" %t1 | FileCheck %s --check-prefix=CHECK4-MINUS
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# RUN: llvm-dwarfdump --name="value5" %t1 | FileCheck %s --check-prefix=CHECK5-MINUS
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# CHECK0-PLUS: : DW_OP_breg2 X2+24)
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# CHECK0-PLUS: DW_AT_type {{.*}}int32_t
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#
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# CHECK1-PLUS: : DW_OP_breg2 X2+16)
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# CHECK1-PLUS: DW_AT_type {{.*}}int32_t
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#
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# CHECK2-PLUS: : DW_OP_breg2 X2+32, DW_OP_lit3, DW_OP_bregx VLENB+0, DW_OP_mul, DW_OP_plus)
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# CHECK2-PLUS: DW_AT_type {{.*}}vint32m1_t
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#
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# CHECK3-PLUS: : DW_OP_breg2 X2+32, DW_OP_lit2, DW_OP_bregx VLENB+0, DW_OP_mul, DW_OP_plus)
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# CHECK3-PLUS: DW_AT_type {{.*}}vint32m1_t
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#
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# CHECK4-PLUS: : DW_OP_breg2 X2+32, DW_OP_lit1, DW_OP_bregx VLENB+0, DW_OP_mul, DW_OP_plus)
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# CHECK4-PLUS: DW_AT_type {{.*}}vbool1_t
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#
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# CHECK5-PLUS: : DW_OP_breg2 X2+32)
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# CHECK5-PLUS: DW_AT_type {{.*}}vbool1_t
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# CHECK0-MINUS: : DW_OP_breg8 X8-40)
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# CHECK0-MINUS: DW_AT_type {{.*}}int32_t
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#
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# CHECK1-MINUS: : DW_OP_breg8 X8-48)
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# CHECK1-MINUS: DW_AT_type {{.*}}int32_t
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#
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# CHECK2-MINUS: : DW_OP_breg8 X8-48, DW_OP_lit1, DW_OP_bregx VLENB+0, DW_OP_mul, DW_OP_minus)
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# CHECK2-MINUS: DW_AT_type {{.*}}vint32m1_t
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#
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# CHECK3-MINUS: : DW_OP_breg8 X8-48, DW_OP_lit2, DW_OP_bregx VLENB+0, DW_OP_mul, DW_OP_minus)
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# CHECK3-MINUS: DW_AT_type {{.*}}vint32m1_t
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#
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# CHECK4-MINUS: : DW_OP_breg8 X8-48, DW_OP_lit3, DW_OP_bregx VLENB+0, DW_OP_mul, DW_OP_minus)
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# CHECK4-MINUS: DW_AT_type {{.*}}vbool1_t
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#
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# CHECK5-MINUS: : DW_OP_breg8 X8-48, DW_OP_lit4, DW_OP_bregx VLENB+0, DW_OP_mul, DW_OP_minus)
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# CHECK5-MINUS: DW_AT_type {{.*}}vbool1_t
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--- |
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define void @foo() !dbg !5 {
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entry:
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unreachable, !dbg !8
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}
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; Function Attrs: nounwind readnone speculatable willreturn
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declare void @llvm.dbg.value(metadata, metadata, metadata)
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!llvm.dbg.cu = !{!0}
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!llvm.debugify = !{!3, !3}
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!llvm.module.flags = !{!4}
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!0 = distinct !DICompileUnit(language: DW_LANG_C, file: !1, producer: "debugify", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2)
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!1 = !DIFile(filename: "debug-info-rvv-dbg-value.mir", directory: "/")
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!2 = !{}
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!3 = !{i32 1}
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!4 = !{i32 2, !"Debug Info Version", i32 3}
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!5 = distinct !DISubprogram(name: "foo", linkageName: "foo", scope: null, file: !1, line: 1, type: !6, scopeLine: 1, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !9)
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!6 = !DISubroutineType(types: !2)
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!7 = !DIBasicType(name: "int32_t", size: 32, encoding: DW_ATE_signed)
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!8 = !DILocation(line: 1, column: 1, scope: !5)
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!9 = !{!10, !11, !12, !13, !14, !15}
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!10 = !DILocalVariable(name: "value0", scope: !5, file: !1, line: 1, type: !7)
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!11 = !DILocalVariable(name: "value1", scope: !5, file: !1, line: 1, type: !7)
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!12 = !DILocalVariable(name: "value2", scope: !5, file: !1, line: 1, type: !16)
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!13 = !DILocalVariable(name: "value3", scope: !5, file: !1, line: 1, type: !16)
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!14 = !DILocalVariable(name: "value4", scope: !5, file: !1, line: 1, type: !21)
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!15 = !DILocalVariable(name: "value5", scope: !5, file: !1, line: 1, type: !21)
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!16 = !DIDerivedType(tag: DW_TAG_typedef, name: "vint32m1_t", file: !1, line: 1, baseType: !17)
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!17 = !DIDerivedType(tag: DW_TAG_typedef, name: "__rvv_int32m1_t", file: !1, baseType: !18)
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!18 = !DICompositeType(tag: DW_TAG_array_type, baseType: !7, flags: DIFlagVector, elements: !19)
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!19 = !{!20}
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!20 = !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_bregx, 7202, 0, DW_OP_constu, 4, DW_OP_div, DW_OP_constu, 1, DW_OP_mul))
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!21 = !DIDerivedType(tag: DW_TAG_typedef, name: "vbool1_t", file: !1, line: 90, baseType: !22)
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!22 = !DIDerivedType(tag: DW_TAG_typedef, name: "__rvv_bool1_t", file: !1, baseType: !23)
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!23 = !DICompositeType(tag: DW_TAG_array_type, baseType: !24, flags: DIFlagVector, elements: !25)
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!24 = !DIBasicType(name: "_Bool", size: 8, encoding: DW_ATE_boolean)
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!25 = !{!26}
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!26 = !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_bregx, 7202, 0, DW_OP_constu, 1, DW_OP_div, DW_OP_constu, 1, DW_OP_mul))
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...
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---
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name: foo
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alignment: 4
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tracksRegLiveness: true
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liveins:
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- { reg: '$x12' }
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- { reg: '$x13' }
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- { reg: '$v8' }
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- { reg: '$v9' }
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- { reg: '$v0' }
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- { reg: '$v1' }
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frameInfo:
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maxAlignment: 16
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adjustsStack: true
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hasCalls: true
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maxCallFrameSize: 0
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localFrameSize: 4
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stack:
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- { id: 0, size: 8, alignment: 8 }
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- { id: 1, size: 8, alignment: 8 }
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- { id: 2, size: 8, alignment: 4, stack-id: scalable-vector }
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- { id: 3, size: 8, alignment: 4, stack-id: scalable-vector }
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- { id: 4, size: 8, alignment: 1, stack-id: scalable-vector }
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- { id: 5, size: 8, alignment: 1, stack-id: scalable-vector }
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machineFunctionInfo: {}
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body: |
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bb.0.entry:
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liveins: $x12, $x13, $v8, $v9, $v0, $v1
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SD killed renamable $x12, %stack.0, 0, debug-location !8
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DBG_VALUE %stack.0, $noreg, !10, !DIExpression(DW_OP_deref), debug-location !8
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SD killed renamable $x13, %stack.1, 0, debug-location !8
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DBG_VALUE %stack.1, $noreg, !11, !DIExpression(DW_OP_deref), debug-location !8
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PseudoVSE32_V_M1 killed renamable $v8, %stack.2, 8, 5, debug-location !DILocation(line: 5, column: 1, scope: !5)
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DBG_VALUE %stack.2, $noreg, !12, !DIExpression(DW_OP_deref), debug-location !DILocation(line: 5, column: 1, scope: !5)
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PseudoVSE32_V_M1 killed renamable $v9, %stack.3, 8, 5, debug-location !DILocation(line: 6, column: 1, scope: !5)
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DBG_VALUE %stack.3, $noreg, !13, !DIExpression(DW_OP_deref), debug-location !DILocation(line: 6, column: 1, scope: !5)
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PseudoVSM_V_B64 killed renamable $v0, %stack.4, 8, 0, debug-location !DILocation(line: 2, column: 1, scope: !5)
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DBG_VALUE %stack.4, $noreg, !14, !DIExpression(DW_OP_deref), debug-location !DILocation(line: 2, column: 1, scope: !5)
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PseudoVSM_V_B64 killed renamable $v1, %stack.5, 8, 0, debug-location !DILocation(line: 3, column: 1, scope: !5)
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DBG_VALUE %stack.5, $noreg, !15, !DIExpression(DW_OP_deref), debug-location !DILocation(line: 3, column: 1, scope: !5)
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PseudoRET
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...
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