forked from OSchip/llvm-project
Add runtime support for __cpu_model (__builtin_cpu_supports)
Summary: This aims to add support for __cpu_model and address Bug 25510. It uses the code from lib/Support/Host.cpp for cpu detection, and creates __cpu_model with that info. Tested on OSX, it builts successfully, but the current version does *not* resolve Bug 25510. The __cpu_model symbol is present in the library but it only gets loaded with -all_load. This patch will not land until this issue is clarified. Built on Linux as well (though libgcc is the default). The use of "asm" required -std=gnu99, hence the cmake change. Corrections on better addressing this are welcome. Note: See additional comments on D20988 (committed as r271921). Reviewers: llvm-commits, joerg, echristo, mehdi_amini Subscribers: mehdi_amini Differential Revision: http://reviews.llvm.org/D21033 llvm-svn: 274865
This commit is contained in:
parent
46df968326
commit
b0b29c958a
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@ -48,6 +48,7 @@ set(GENERIC_SOURCES
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cmpti2.c
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comparedf2.c
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comparesf2.c
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cpu_model.c
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ctzdi2.c
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ctzsi2.c
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ctzti2.c
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@ -392,7 +393,7 @@ if (APPLE)
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add_subdirectory(macho_embedded)
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darwin_add_builtin_libraries(${BUILTIN_SUPPORTED_OS})
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else ()
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append_string_if(COMPILER_RT_HAS_STD_C99_FLAG -std=c99 maybe_stdc99)
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append_string_if(COMPILER_RT_HAS_STD_C99_FLAG -std=gnu99 maybe_stdc99)
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foreach (arch ${BUILTIN_SUPPORTED_ARCH})
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if (CAN_TARGET_${arch})
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@ -0,0 +1,769 @@
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//===-- cpu_model.c - Support for __cpu_model builtin ------------*- C -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file is based on LLVM's lib/Support/Host.cpp.
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// It implements the operating system Host concept and builtin
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// __cpu_model for the compiler_rt library.
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//
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//===----------------------------------------------------------------------===//
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#include <assert.h>
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#define bool int
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#define true 1
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#define false 0
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#ifdef _MSC_VER
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#include <intrin.h>
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#endif
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enum VendorSignatures {
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SIG_INTEL = 0x756e6547 /* Genu */,
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SIG_AMD = 0x68747541 /* Auth */
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};
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enum ProcessorVendors {
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VENDOR_INTEL = 1,
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VENDOR_AMD,
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VENDOR_OTHER,
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VENDOR_MAX
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};
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enum ProcessorTypes {
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INTEL_ATOM = 1,
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INTEL_CORE2,
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INTEL_COREI7,
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AMDFAM10H,
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AMDFAM15H,
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INTEL_i386,
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INTEL_i486,
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INTEL_PENTIUM,
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INTEL_PENTIUM_PRO,
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INTEL_PENTIUM_II,
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INTEL_PENTIUM_III,
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INTEL_PENTIUM_IV,
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INTEL_PENTIUM_M,
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INTEL_CORE_DUO,
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INTEL_XEONPHI,
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INTEL_X86_64,
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INTEL_NOCONA,
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INTEL_PRESCOTT,
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AMD_i486,
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AMDPENTIUM,
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AMDATHLON,
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AMDFAM14H,
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AMDFAM16H,
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CPU_TYPE_MAX
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};
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enum ProcessorSubtypes {
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INTEL_COREI7_NEHALEM = 1,
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INTEL_COREI7_WESTMERE,
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INTEL_COREI7_SANDYBRIDGE,
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AMDFAM10H_BARCELONA,
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AMDFAM10H_SHANGHAI,
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AMDFAM10H_ISTANBUL,
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AMDFAM15H_BDVER1,
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AMDFAM15H_BDVER2,
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INTEL_PENTIUM_MMX,
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INTEL_CORE2_65,
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INTEL_CORE2_45,
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INTEL_COREI7_IVYBRIDGE,
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INTEL_COREI7_HASWELL,
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INTEL_COREI7_BROADWELL,
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INTEL_COREI7_SKYLAKE,
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INTEL_COREI7_SKYLAKE_AVX512,
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INTEL_ATOM_BONNELL,
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INTEL_ATOM_SILVERMONT,
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INTEL_KNIGHTS_LANDING,
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AMDPENTIUM_K6,
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AMDPENTIUM_K62,
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AMDPENTIUM_K63,
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AMDPENTIUM_GEODE,
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AMDATHLON_TBIRD,
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AMDATHLON_MP,
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AMDATHLON_XP,
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AMDATHLON_K8SSE3,
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AMDATHLON_OPTERON,
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AMDATHLON_FX,
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AMDATHLON_64,
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AMD_BTVER1,
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AMD_BTVER2,
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AMDFAM15H_BDVER3,
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AMDFAM15H_BDVER4,
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CPU_SUBTYPE_MAX
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};
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enum ProcessorFeatures {
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FEATURE_CMOV = 0,
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FEATURE_MMX,
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FEATURE_POPCNT,
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FEATURE_SSE,
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FEATURE_SSE2,
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FEATURE_SSE3,
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FEATURE_SSSE3,
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FEATURE_SSE4_1,
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FEATURE_SSE4_2,
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FEATURE_AVX,
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FEATURE_AVX2,
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FEATURE_AVX512,
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FEATURE_AVX512SAVE,
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FEATURE_MOVBE,
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FEATURE_ADX,
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FEATURE_EM64T
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};
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#if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\
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|| defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
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/// getX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in
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/// the specified arguments. If we can't run cpuid on the host, return true.
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static bool getX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
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unsigned *rECX, unsigned *rEDX) {
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#if defined(__GNUC__) || defined(__clang__)
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#if defined(__x86_64__) || defined(_M_AMD64) || defined(_M_X64)
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// gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
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asm("movq\t%%rbx, %%rsi\n\t"
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"cpuid\n\t"
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"xchgq\t%%rbx, %%rsi\n\t"
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: "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
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: "a"(value));
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return false;
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#elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
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asm("movl\t%%ebx, %%esi\n\t"
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"cpuid\n\t"
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"xchgl\t%%ebx, %%esi\n\t"
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: "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
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: "a"(value));
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return false;
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// pedantic #else returns to appease -Wunreachable-code (so we don't generate
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// postprocessed code that looks like "return true; return false;")
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#else
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return true;
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#endif
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#elif defined(_MSC_VER)
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// The MSVC intrinsic is portable across x86 and x64.
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int registers[4];
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__cpuid(registers, value);
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*rEAX = registers[0];
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*rEBX = registers[1];
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*rECX = registers[2];
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*rEDX = registers[3];
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return false;
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#else
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return true;
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#endif
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}
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/// getX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return
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/// the 4 values in the specified arguments. If we can't run cpuid on the host,
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/// return true.
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static bool getX86CpuIDAndInfoEx(unsigned value, unsigned subleaf,
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unsigned *rEAX, unsigned *rEBX, unsigned *rECX,
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unsigned *rEDX) {
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#if defined(__x86_64__) || defined(_M_AMD64) || defined(_M_X64)
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#if defined(__GNUC__)
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// gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
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asm("movq\t%%rbx, %%rsi\n\t"
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"cpuid\n\t"
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"xchgq\t%%rbx, %%rsi\n\t"
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: "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
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: "a"(value), "c"(subleaf));
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return false;
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#elif defined(_MSC_VER)
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int registers[4];
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__cpuidex(registers, value, subleaf);
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*rEAX = registers[0];
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*rEBX = registers[1];
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*rECX = registers[2];
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*rEDX = registers[3];
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return false;
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#else
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return true;
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#endif
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#elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
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#if defined(__GNUC__)
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asm("movl\t%%ebx, %%esi\n\t"
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"cpuid\n\t"
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"xchgl\t%%ebx, %%esi\n\t"
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: "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
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: "a"(value), "c"(subleaf));
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return false;
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#elif defined(_MSC_VER)
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__asm {
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mov eax,value
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mov ecx,subleaf
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cpuid
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mov esi,rEAX
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mov dword ptr [esi],eax
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mov esi,rEBX
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mov dword ptr [esi],ebx
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mov esi,rECX
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mov dword ptr [esi],ecx
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mov esi,rEDX
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mov dword ptr [esi],edx
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}
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return false;
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#else
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return true;
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#endif
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#else
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return true;
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#endif
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}
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static bool getX86XCR0(unsigned *rEAX, unsigned *rEDX) {
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#if defined(__GNUC__)
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// Check xgetbv; this uses a .byte sequence instead of the instruction
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// directly because older assemblers do not include support for xgetbv and
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// there is no easy way to conditionally compile based on the assembler used.
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__asm__(".byte 0x0f, 0x01, 0xd0" : "=a"(*rEAX), "=d"(*rEDX) : "c"(0));
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return false;
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#elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK)
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unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
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*rEAX = Result;
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*rEDX = Result >> 32;
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return false;
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#else
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return true;
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#endif
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}
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#endif
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static void detectX86FamilyModel(unsigned EAX, unsigned *Family,
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unsigned *Model) {
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*Family = (EAX >> 8) & 0xf; // Bits 8 - 11
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*Model = (EAX >> 4) & 0xf; // Bits 4 - 7
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if (*Family == 6 || *Family == 0xf) {
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if (*Family == 0xf)
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// Examine extended family ID if family ID is F.
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*Family += (EAX >> 20) & 0xff; // Bits 20 - 27
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// Examine extended model ID if family ID is 6 or F.
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*Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
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}
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}
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static void
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getIntelProcessorTypeAndSubtype(unsigned int Family, unsigned int Model,
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unsigned int Brand_id, unsigned int Features,
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unsigned *Type, unsigned *Subtype) {
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if (Brand_id != 0)
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return;
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switch (Family) {
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case 3:
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*Type = INTEL_i386;
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break;
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case 4:
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switch (Model) {
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case 0: // Intel486 DX processors
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case 1: // Intel486 DX processors
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case 2: // Intel486 SX processors
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case 3: // Intel487 processors, IntelDX2 OverDrive processors,
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// IntelDX2 processors
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case 4: // Intel486 SL processor
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case 5: // IntelSX2 processors
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case 7: // Write-Back Enhanced IntelDX2 processors
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case 8: // IntelDX4 OverDrive processors, IntelDX4 processors
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default:
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*Type = INTEL_i486;
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break;
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}
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case 5:
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switch (Model) {
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case 1: // Pentium OverDrive processor for Pentium processor (60, 66),
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// Pentium processors (60, 66)
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case 2: // Pentium OverDrive processor for Pentium processor (75, 90,
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// 100, 120, 133), Pentium processors (75, 90, 100, 120, 133,
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// 150, 166, 200)
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case 3: // Pentium OverDrive processors for Intel486 processor-based
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// systems
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*Type = INTEL_PENTIUM;
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break;
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case 4: // Pentium OverDrive processor with MMX technology for Pentium
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// processor (75, 90, 100, 120, 133), Pentium processor with
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// MMX technology (166, 200)
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*Type = INTEL_PENTIUM;
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*Subtype = INTEL_PENTIUM_MMX;
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break;
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default:
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*Type = INTEL_PENTIUM;
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break;
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}
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case 6:
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switch (Model) {
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case 0x01: // Pentium Pro processor
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*Type = INTEL_PENTIUM_PRO;
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break;
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case 0x03: // Intel Pentium II OverDrive processor, Pentium II processor,
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// model 03
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case 0x05: // Pentium II processor, model 05, Pentium II Xeon processor,
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// model 05, and Intel Celeron processor, model 05
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case 0x06: // Celeron processor, model 06
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*Type = INTEL_PENTIUM_II;
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break;
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case 0x07: // Pentium III processor, model 07, and Pentium III Xeon
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// processor, model 07
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case 0x08: // Pentium III processor, model 08, Pentium III Xeon processor,
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// model 08, and Celeron processor, model 08
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case 0x0a: // Pentium III Xeon processor, model 0Ah
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case 0x0b: // Pentium III processor, model 0Bh
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*Type = INTEL_PENTIUM_III;
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break;
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case 0x09: // Intel Pentium M processor, Intel Celeron M processor model 09.
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case 0x0d: // Intel Pentium M processor, Intel Celeron M processor, model
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// 0Dh. All processors are manufactured using the 90 nm process.
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case 0x15: // Intel EP80579 Integrated Processor and Intel EP80579
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// Integrated Processor with Intel QuickAssist Technology
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*Type = INTEL_PENTIUM_M;
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break;
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case 0x0e: // Intel Core Duo processor, Intel Core Solo processor, model
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// 0Eh. All processors are manufactured using the 65 nm process.
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*Type = INTEL_CORE_DUO;
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break; // yonah
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case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile
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// processor, Intel Core 2 Quad processor, Intel Core 2 Quad
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// mobile processor, Intel Core 2 Extreme processor, Intel
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// Pentium Dual-Core processor, Intel Xeon processor, model
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// 0Fh. All processors are manufactured using the 65 nm process.
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case 0x16: // Intel Celeron processor model 16h. All processors are
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// manufactured using the 65 nm process
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*Type = INTEL_CORE2; // "core2"
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*Subtype = INTEL_CORE2_65;
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break;
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case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model
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// 17h. All processors are manufactured using the 45 nm process.
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//
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// 45nm: Penryn , Wolfdale, Yorkfield (XE)
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case 0x1d: // Intel Xeon processor MP. All processors are manufactured using
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// the 45 nm process.
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*Type = INTEL_CORE2; // "penryn"
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*Subtype = INTEL_CORE2_45;
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break;
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case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All
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// processors are manufactured using the 45 nm process.
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case 0x1e: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz.
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// As found in a Summer 2010 model iMac.
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case 0x1f:
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case 0x2e: // Nehalem EX
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*Type = INTEL_COREI7; // "nehalem"
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*Subtype = INTEL_COREI7_NEHALEM;
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break;
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case 0x25: // Intel Core i7, laptop version.
|
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case 0x2c: // Intel Core i7 processor and Intel Xeon processor. All
|
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// processors are manufactured using the 32 nm process.
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case 0x2f: // Westmere EX
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*Type = INTEL_COREI7; // "westmere"
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*Subtype = INTEL_COREI7_WESTMERE;
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break;
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case 0x2a: // Intel Core i7 processor. All processors are manufactured
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// using the 32 nm process.
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case 0x2d:
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*Type = INTEL_COREI7; //"sandybridge"
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*Subtype = INTEL_COREI7_SANDYBRIDGE;
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break;
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case 0x3a:
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case 0x3e: // Ivy Bridge EP
|
||||
*Type = INTEL_COREI7; // "ivybridge"
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*Subtype = INTEL_COREI7_IVYBRIDGE;
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break;
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// Haswell:
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case 0x3c:
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case 0x3f:
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case 0x45:
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case 0x46:
|
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*Type = INTEL_COREI7; // "haswell"
|
||||
*Subtype = INTEL_COREI7_HASWELL;
|
||||
break;
|
||||
|
||||
// Broadwell:
|
||||
case 0x3d:
|
||||
case 0x47:
|
||||
case 0x4f:
|
||||
case 0x56:
|
||||
*Type = INTEL_COREI7; // "broadwell"
|
||||
*Subtype = INTEL_COREI7_BROADWELL;
|
||||
break;
|
||||
|
||||
// Skylake:
|
||||
case 0x4e:
|
||||
*Type = INTEL_COREI7; // "skylake-avx512"
|
||||
*Subtype = INTEL_COREI7_SKYLAKE_AVX512;
|
||||
break;
|
||||
case 0x5e:
|
||||
*Type = INTEL_COREI7; // "skylake"
|
||||
*Subtype = INTEL_COREI7_SKYLAKE;
|
||||
break;
|
||||
|
||||
case 0x1c: // Most 45 nm Intel Atom processors
|
||||
case 0x26: // 45 nm Atom Lincroft
|
||||
case 0x27: // 32 nm Atom Medfield
|
||||
case 0x35: // 32 nm Atom Midview
|
||||
case 0x36: // 32 nm Atom Midview
|
||||
*Type = INTEL_ATOM;
|
||||
*Subtype = INTEL_ATOM_BONNELL;
|
||||
break; // "bonnell"
|
||||
|
||||
// Atom Silvermont codes from the Intel software optimization guide.
|
||||
case 0x37:
|
||||
case 0x4a:
|
||||
case 0x4d:
|
||||
case 0x5a:
|
||||
case 0x5d:
|
||||
case 0x4c: // really airmont
|
||||
*Type = INTEL_ATOM;
|
||||
*Subtype = INTEL_ATOM_SILVERMONT;
|
||||
break; // "silvermont"
|
||||
|
||||
case 0x57:
|
||||
*Type = INTEL_XEONPHI; // knl
|
||||
*Subtype = INTEL_KNIGHTS_LANDING;
|
||||
break;
|
||||
|
||||
default: // Unknown family 6 CPU, try to guess.
|
||||
if (Features & (1 << FEATURE_AVX512)) {
|
||||
*Type = INTEL_XEONPHI; // knl
|
||||
*Subtype = INTEL_KNIGHTS_LANDING;
|
||||
break;
|
||||
}
|
||||
if (Features & (1 << FEATURE_ADX)) {
|
||||
*Type = INTEL_COREI7;
|
||||
*Subtype = INTEL_COREI7_BROADWELL;
|
||||
break;
|
||||
}
|
||||
if (Features & (1 << FEATURE_AVX2)) {
|
||||
*Type = INTEL_COREI7;
|
||||
*Subtype = INTEL_COREI7_HASWELL;
|
||||
break;
|
||||
}
|
||||
if (Features & (1 << FEATURE_AVX)) {
|
||||
*Type = INTEL_COREI7;
|
||||
*Subtype = INTEL_COREI7_SANDYBRIDGE;
|
||||
break;
|
||||
}
|
||||
if (Features & (1 << FEATURE_SSE4_2)) {
|
||||
if (Features & (1 << FEATURE_MOVBE)) {
|
||||
*Type = INTEL_ATOM;
|
||||
*Subtype = INTEL_ATOM_SILVERMONT;
|
||||
} else {
|
||||
*Type = INTEL_COREI7;
|
||||
*Subtype = INTEL_COREI7_NEHALEM;
|
||||
}
|
||||
break;
|
||||
}
|
||||
if (Features & (1 << FEATURE_SSE4_1)) {
|
||||
*Type = INTEL_CORE2; // "penryn"
|
||||
*Subtype = INTEL_CORE2_45;
|
||||
break;
|
||||
}
|
||||
if (Features & (1 << FEATURE_SSSE3)) {
|
||||
if (Features & (1 << FEATURE_MOVBE)) {
|
||||
*Type = INTEL_ATOM;
|
||||
*Subtype = INTEL_ATOM_BONNELL; // "bonnell"
|
||||
} else {
|
||||
*Type = INTEL_CORE2; // "core2"
|
||||
*Subtype = INTEL_CORE2_65;
|
||||
}
|
||||
break;
|
||||
}
|
||||
if (Features & (1 << FEATURE_EM64T)) {
|
||||
*Type = INTEL_X86_64;
|
||||
break; // x86-64
|
||||
}
|
||||
if (Features & (1 << FEATURE_SSE2)) {
|
||||
*Type = INTEL_PENTIUM_M;
|
||||
break;
|
||||
}
|
||||
if (Features & (1 << FEATURE_SSE)) {
|
||||
*Type = INTEL_PENTIUM_III;
|
||||
break;
|
||||
}
|
||||
if (Features & (1 << FEATURE_MMX)) {
|
||||
*Type = INTEL_PENTIUM_II;
|
||||
break;
|
||||
}
|
||||
*Type = INTEL_PENTIUM_PRO;
|
||||
break;
|
||||
}
|
||||
case 15: {
|
||||
switch (Model) {
|
||||
case 0: // Pentium 4 processor, Intel Xeon processor. All processors are
|
||||
// model 00h and manufactured using the 0.18 micron process.
|
||||
case 1: // Pentium 4 processor, Intel Xeon processor, Intel Xeon
|
||||
// processor MP, and Intel Celeron processor. All processors are
|
||||
// model 01h and manufactured using the 0.18 micron process.
|
||||
case 2: // Pentium 4 processor, Mobile Intel Pentium 4 processor - M,
|
||||
// Intel Xeon processor, Intel Xeon processor MP, Intel Celeron
|
||||
// processor, and Mobile Intel Celeron processor. All processors
|
||||
// are model 02h and manufactured using the 0.13 micron process.
|
||||
*Type =
|
||||
((Features & (1 << FEATURE_EM64T)) ? INTEL_X86_64 : INTEL_PENTIUM_IV);
|
||||
break;
|
||||
|
||||
case 3: // Pentium 4 processor, Intel Xeon processor, Intel Celeron D
|
||||
// processor. All processors are model 03h and manufactured using
|
||||
// the 90 nm process.
|
||||
case 4: // Pentium 4 processor, Pentium 4 processor Extreme Edition,
|
||||
// Pentium D processor, Intel Xeon processor, Intel Xeon
|
||||
// processor MP, Intel Celeron D processor. All processors are
|
||||
// model 04h and manufactured using the 90 nm process.
|
||||
case 6: // Pentium 4 processor, Pentium D processor, Pentium processor
|
||||
// Extreme Edition, Intel Xeon processor, Intel Xeon processor
|
||||
// MP, Intel Celeron D processor. All processors are model 06h
|
||||
// and manufactured using the 65 nm process.
|
||||
*Type =
|
||||
((Features & (1 << FEATURE_EM64T)) ? INTEL_NOCONA : INTEL_PRESCOTT);
|
||||
break;
|
||||
|
||||
default:
|
||||
*Type =
|
||||
((Features & (1 << FEATURE_EM64T)) ? INTEL_X86_64 : INTEL_PENTIUM_IV);
|
||||
break;
|
||||
}
|
||||
}
|
||||
default:
|
||||
break; /*"generic"*/
|
||||
}
|
||||
}
|
||||
|
||||
static void getAMDProcessorTypeAndSubtype(unsigned int Family,
|
||||
unsigned int Model,
|
||||
unsigned int Features,
|
||||
unsigned *Type,
|
||||
unsigned *Subtype) {
|
||||
// FIXME: this poorly matches the generated SubtargetFeatureKV table. There
|
||||
// appears to be no way to generate the wide variety of AMD-specific targets
|
||||
// from the information returned from CPUID.
|
||||
switch (Family) {
|
||||
case 4:
|
||||
*Type = AMD_i486;
|
||||
case 5:
|
||||
*Type = AMDPENTIUM;
|
||||
switch (Model) {
|
||||
case 6:
|
||||
case 7:
|
||||
*Subtype = AMDPENTIUM_K6;
|
||||
break; // "k6"
|
||||
case 8:
|
||||
*Subtype = AMDPENTIUM_K62;
|
||||
break; // "k6-2"
|
||||
case 9:
|
||||
case 13:
|
||||
*Subtype = AMDPENTIUM_K63;
|
||||
break; // "k6-3"
|
||||
case 10:
|
||||
*Subtype = AMDPENTIUM_GEODE;
|
||||
break; // "geode"
|
||||
default:
|
||||
break;
|
||||
}
|
||||
case 6:
|
||||
*Type = AMDATHLON;
|
||||
switch (Model) {
|
||||
case 4:
|
||||
*Subtype = AMDATHLON_TBIRD;
|
||||
break; // "athlon-tbird"
|
||||
case 6:
|
||||
case 7:
|
||||
case 8:
|
||||
*Subtype = AMDATHLON_MP;
|
||||
break; // "athlon-mp"
|
||||
case 10:
|
||||
*Subtype = AMDATHLON_XP;
|
||||
break; // "athlon-xp"
|
||||
default:
|
||||
break;
|
||||
}
|
||||
case 15:
|
||||
*Type = AMDATHLON;
|
||||
if (Features & (1 << FEATURE_SSE3)) {
|
||||
*Subtype = AMDATHLON_K8SSE3;
|
||||
break; // "k8-sse3"
|
||||
}
|
||||
switch (Model) {
|
||||
case 1:
|
||||
*Subtype = AMDATHLON_OPTERON;
|
||||
break; // "opteron"
|
||||
case 5:
|
||||
*Subtype = AMDATHLON_FX;
|
||||
break; // "athlon-fx"; also opteron
|
||||
default:
|
||||
*Subtype = AMDATHLON_64;
|
||||
break; // "athlon64"
|
||||
}
|
||||
case 16:
|
||||
*Type = AMDFAM10H; // "amdfam10"
|
||||
switch (Model) {
|
||||
case 2:
|
||||
*Subtype = AMDFAM10H_BARCELONA;
|
||||
break;
|
||||
case 4:
|
||||
*Subtype = AMDFAM10H_SHANGHAI;
|
||||
break;
|
||||
case 8:
|
||||
*Subtype = AMDFAM10H_ISTANBUL;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
case 20:
|
||||
*Type = AMDFAM14H;
|
||||
*Subtype = AMD_BTVER1;
|
||||
break; // "btver1";
|
||||
case 21:
|
||||
*Type = AMDFAM15H;
|
||||
if (!(Features &
|
||||
(1 << FEATURE_AVX))) { // If no AVX support, provide a sane fallback.
|
||||
*Subtype = AMD_BTVER1;
|
||||
break; // "btver1"
|
||||
}
|
||||
if (Model >= 0x50 && Model <= 0x6f) {
|
||||
*Subtype = AMDFAM15H_BDVER4;
|
||||
break; // "bdver4"; 50h-6Fh: Excavator
|
||||
}
|
||||
if (Model >= 0x30 && Model <= 0x3f) {
|
||||
*Subtype = AMDFAM15H_BDVER3;
|
||||
break; // "bdver3"; 30h-3Fh: Steamroller
|
||||
}
|
||||
if (Model >= 0x10 && Model <= 0x1f) {
|
||||
*Subtype = AMDFAM15H_BDVER2;
|
||||
break; // "bdver2"; 10h-1Fh: Piledriver
|
||||
}
|
||||
if (Model <= 0x0f) {
|
||||
*Subtype = AMDFAM15H_BDVER1;
|
||||
break; // "bdver1"; 00h-0Fh: Bulldozer
|
||||
}
|
||||
break;
|
||||
case 22:
|
||||
*Type = AMDFAM16H;
|
||||
if (!(Features &
|
||||
(1 << FEATURE_AVX))) { // If no AVX support provide a sane fallback.
|
||||
*Subtype = AMD_BTVER1;
|
||||
break; // "btver1";
|
||||
}
|
||||
*Subtype = AMD_BTVER2;
|
||||
break; // "btver2"
|
||||
default:
|
||||
break; // "generic"
|
||||
}
|
||||
}
|
||||
|
||||
unsigned getAvailableFeatures(unsigned int ECX, unsigned int EDX,
|
||||
unsigned MaxLeaf) {
|
||||
unsigned Features = 0;
|
||||
unsigned int EAX, EBX;
|
||||
Features |= (((EDX >> 23) & 1) << FEATURE_MMX);
|
||||
Features |= (((EDX >> 25) & 1) << FEATURE_SSE);
|
||||
Features |= (((EDX >> 26) & 1) << FEATURE_SSE2);
|
||||
Features |= (((ECX >> 0) & 1) << FEATURE_SSE3);
|
||||
Features |= (((ECX >> 9) & 1) << FEATURE_SSSE3);
|
||||
Features |= (((ECX >> 19) & 1) << FEATURE_SSE4_1);
|
||||
Features |= (((ECX >> 20) & 1) << FEATURE_SSE4_2);
|
||||
Features |= (((ECX >> 22) & 1) << FEATURE_MOVBE);
|
||||
|
||||
// If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
|
||||
// indicates that the AVX registers will be saved and restored on context
|
||||
// switch, then we have full AVX support.
|
||||
const unsigned AVXBits = (1 << 27) | (1 << 28);
|
||||
bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) &&
|
||||
((EAX & 0x6) == 0x6);
|
||||
bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0);
|
||||
bool HasLeaf7 =
|
||||
MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
|
||||
bool HasADX = HasLeaf7 && ((EBX >> 19) & 1);
|
||||
bool HasAVX2 = HasAVX && HasLeaf7 && (EBX & 0x20);
|
||||
bool HasAVX512 = HasLeaf7 && HasAVX512Save && ((EBX >> 16) & 1);
|
||||
Features |= (HasAVX << FEATURE_AVX);
|
||||
Features |= (HasAVX2 << FEATURE_AVX2);
|
||||
Features |= (HasAVX512 << FEATURE_AVX512);
|
||||
Features |= (HasAVX512Save << FEATURE_AVX512SAVE);
|
||||
Features |= (HasADX << FEATURE_ADX);
|
||||
|
||||
getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
|
||||
Features |= (((EDX >> 29) & 0x1) << FEATURE_EM64T);
|
||||
return Features;
|
||||
}
|
||||
|
||||
#ifdef HAVE_INIT_PRIORITY
|
||||
#define CONSTRUCTOR_PRIORITY (101)
|
||||
#else
|
||||
#define CONSTRUCTOR_PRIORITY
|
||||
#endif
|
||||
|
||||
int __cpu_indicator_init (void)
|
||||
__attribute__ ((constructor CONSTRUCTOR_PRIORITY));
|
||||
|
||||
struct __processor_model
|
||||
{
|
||||
unsigned int __cpu_vendor;
|
||||
unsigned int __cpu_type;
|
||||
unsigned int __cpu_subtype;
|
||||
unsigned int __cpu_features[1];
|
||||
} __cpu_model;
|
||||
|
||||
|
||||
/* A constructor function that is sets __cpu_model and __cpu_features with
|
||||
the right values. This needs to run only once. This constructor is
|
||||
given the highest priority and it should run before constructors without
|
||||
the priority set. However, it still runs after ifunc initializers and
|
||||
needs to be called explicitly there. */
|
||||
|
||||
int __attribute__ ((constructor CONSTRUCTOR_PRIORITY))
|
||||
__cpu_indicator_init (void)
|
||||
{
|
||||
unsigned int EAX, EBX, ECX, EDX;
|
||||
unsigned int MaxLeaf = 5;
|
||||
unsigned int Vendor;
|
||||
unsigned int Model, Family, Brand_id;
|
||||
unsigned int Features = 0;
|
||||
|
||||
/* This function needs to run just once. */
|
||||
if (__cpu_model.__cpu_vendor)
|
||||
return 0;
|
||||
|
||||
/* Assume cpuid insn present. Run in level 0 to get vendor id. */
|
||||
if (getX86CpuIDAndInfo (0, &MaxLeaf, &Vendor, &ECX, &EDX)) {
|
||||
__cpu_model.__cpu_vendor = VENDOR_OTHER;
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (MaxLeaf < 1 || getX86CpuIDAndInfo (1, &EAX, &EBX, &ECX, &EDX)) {
|
||||
__cpu_model.__cpu_vendor = VENDOR_OTHER;
|
||||
return -1;
|
||||
}
|
||||
|
||||
detectX86FamilyModel(EAX, &Family, &Model);
|
||||
Brand_id = EBX & 0xff;
|
||||
|
||||
/* Find available features. */
|
||||
Features = getAvailableFeatures (ECX, EDX, MaxLeaf);
|
||||
__cpu_model.__cpu_features[0] = Features;
|
||||
|
||||
if (Vendor == SIG_INTEL) {
|
||||
/* Get CPU type. */
|
||||
getIntelProcessorTypeAndSubtype (Family, Model, Brand_id, Features, &(__cpu_model.__cpu_type), &(__cpu_model.__cpu_subtype));
|
||||
__cpu_model.__cpu_vendor = VENDOR_INTEL;
|
||||
}
|
||||
else if (Vendor == SIG_AMD) {
|
||||
/* Get CPU type. */
|
||||
getAMDProcessorTypeAndSubtype (Family, Model, Features, &(__cpu_model.__cpu_type), &(__cpu_model.__cpu_subtype));
|
||||
__cpu_model.__cpu_vendor = VENDOR_AMD;
|
||||
}
|
||||
else
|
||||
__cpu_model.__cpu_vendor = VENDOR_OTHER;
|
||||
|
||||
assert (__cpu_model.__cpu_vendor < VENDOR_MAX);
|
||||
assert (__cpu_model.__cpu_type < CPU_TYPE_MAX);
|
||||
assert (__cpu_model.__cpu_subtype < CPU_SUBTYPE_MAX);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
Loading…
Reference in New Issue