forked from OSchip/llvm-project
[AArch64][SVE] Add some integer DestructiveBinaryComm* patterns
Add DestructiveBinaryComm* patterns for ADD, SUB, and SUBR. Differential Revision: https://reviews.llvm.org/D76711
This commit is contained in:
Cameron McInally
parent
184b383457
commit
b085e51d81
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@ -199,9 +199,13 @@ let Predicates = [HasSVE] in {
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defm EOR_ZZZ : sve_int_bin_cons_log<0b10, "eor", xor>;
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defm BIC_ZZZ : sve_int_bin_cons_log<0b11, "bic", null_frag>;
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defm ADD_ZPmZ : sve_int_bin_pred_arit_0<0b000, "add", int_aarch64_sve_add>;
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defm SUB_ZPmZ : sve_int_bin_pred_arit_0<0b001, "sub", int_aarch64_sve_sub>;
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defm SUBR_ZPmZ : sve_int_bin_pred_arit_0<0b011, "subr", int_aarch64_sve_subr>;
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defm ADD_ZPmZ : sve_int_bin_pred_arit_0<0b000, "add", "ADD_ZPZZ", int_aarch64_sve_add, DestructiveBinaryComm>;
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defm SUB_ZPmZ : sve_int_bin_pred_arit_0<0b001, "sub", "SUB_ZPZZ", int_aarch64_sve_sub, DestructiveBinaryCommWithRev, "SUBR_ZPmZ", 1>;
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defm SUBR_ZPmZ : sve_int_bin_pred_arit_0<0b011, "subr", "SUBR_ZPZZ", int_aarch64_sve_subr, DestructiveBinaryCommWithRev, "SUB_ZPmZ", 0>;
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defm ADD_ZPZZ : sve_int_bin_pred_zx<int_aarch64_sve_add>;
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defm SUB_ZPZZ : sve_int_bin_pred_zx<int_aarch64_sve_sub>;
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defm SUBR_ZPZZ : sve_int_bin_pred_zx<int_aarch64_sve_subr>;
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defm ORR_ZPmZ : sve_int_bin_pred_log<0b000, "orr", int_aarch64_sve_orr>;
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defm EOR_ZPmZ : sve_int_bin_pred_log<0b001, "eor", int_aarch64_sve_eor>;
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@ -2341,11 +2341,20 @@ multiclass sve_int_bin_pred_log<bits<3> opc, string asm, SDPatternOperator op> {
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def : SVE_3_Op_Pat<nxv2i64, op, nxv2i1, nxv2i64, nxv2i64, !cast<Instruction>(NAME # _D)>;
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}
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multiclass sve_int_bin_pred_arit_0<bits<3> opc, string asm, SDPatternOperator op> {
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def _B : sve_int_bin_pred_arit_log<0b00, 0b00, opc, asm, ZPR8>;
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def _H : sve_int_bin_pred_arit_log<0b01, 0b00, opc, asm, ZPR16>;
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def _S : sve_int_bin_pred_arit_log<0b10, 0b00, opc, asm, ZPR32>;
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def _D : sve_int_bin_pred_arit_log<0b11, 0b00, opc, asm, ZPR64>;
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multiclass sve_int_bin_pred_arit_0<bits<3> opc, string asm, string Ps,
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SDPatternOperator op,
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DestructiveInstTypeEnum flags,
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string revname="", bit isOrig=0> {
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let DestructiveInstType = flags in {
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def _B : sve_int_bin_pred_arit_log<0b00, 0b00, opc, asm, ZPR8>,
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SVEPseudo2Instr<Ps # _B, 1>, SVEInstr2Rev<NAME # _B, revname # _B, isOrig>;
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def _H : sve_int_bin_pred_arit_log<0b01, 0b00, opc, asm, ZPR16>,
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SVEPseudo2Instr<Ps # _H, 1>, SVEInstr2Rev<NAME # _H, revname # _H, isOrig>;
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def _S : sve_int_bin_pred_arit_log<0b10, 0b00, opc, asm, ZPR32>,
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SVEPseudo2Instr<Ps # _S, 1>, SVEInstr2Rev<NAME # _S, revname # _S, isOrig>;
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def _D : sve_int_bin_pred_arit_log<0b11, 0b00, opc, asm, ZPR64>,
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SVEPseudo2Instr<Ps # _D, 1>, SVEInstr2Rev<NAME # _D, revname # _D, isOrig>;
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}
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def : SVE_3_Op_Pat<nxv16i8, op, nxv16i1, nxv16i8, nxv16i8, !cast<Instruction>(NAME # _B)>;
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def : SVE_3_Op_Pat<nxv8i16, op, nxv8i1, nxv8i16, nxv8i16, !cast<Instruction>(NAME # _H)>;
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@ -0,0 +1,172 @@
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; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
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;
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; ADD
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;
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define <vscale x 16 x i8> @add_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
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; CHECK-LABEL: add_i8:
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; CHECK: movprfx z0.b, p0/z, z0.b
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; CHECK-NEXT: add z0.b, p0/m, z0.b, z1.b
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; CHECK-NEXT: ret
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%a_z = select <vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> zeroinitializer
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%out = call <vscale x 16 x i8> @llvm.aarch64.sve.add.nxv16i8(<vscale x 16 x i1> %pg,
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<vscale x 16 x i8> %a_z,
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<vscale x 16 x i8> %b)
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ret <vscale x 16 x i8> %out
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}
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define <vscale x 8 x i16> @add_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
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; CHECK-LABEL: add_i16:
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; CHECK: movprfx z0.h, p0/z, z0.h
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; CHECK-NEXT: add z0.h, p0/m, z0.h, z1.h
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; CHECK-NEXT: ret
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%a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> zeroinitializer
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%out = call <vscale x 8 x i16> @llvm.aarch64.sve.add.nxv8i16(<vscale x 8 x i1> %pg,
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<vscale x 8 x i16> %a_z,
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<vscale x 8 x i16> %b)
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ret <vscale x 8 x i16> %out
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}
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define <vscale x 4 x i32> @add_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
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; CHECK-LABEL: add_i32:
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; CHECK: movprfx z0.s, p0/z, z0.s
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; CHECK-NEXT: add z0.s, p0/m, z0.s, z1.s
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; CHECK-NEXT: ret
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%a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> zeroinitializer
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%out = call <vscale x 4 x i32> @llvm.aarch64.sve.add.nxv4i32(<vscale x 4 x i1> %pg,
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<vscale x 4 x i32> %a_z,
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<vscale x 4 x i32> %b)
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ret <vscale x 4 x i32> %out
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}
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define <vscale x 2 x i64> @add_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
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; CHECK-LABEL: add_i64:
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; CHECK: movprfx z0.d, p0/z, z0.d
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; CHECK-NEXT: add z0.d, p0/m, z0.d, z1.d
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; CHECK-NEXT: ret
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%a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> zeroinitializer
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%out = call <vscale x 2 x i64> @llvm.aarch64.sve.add.nxv2i64(<vscale x 2 x i1> %pg,
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<vscale x 2 x i64> %a_z,
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<vscale x 2 x i64> %b)
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ret <vscale x 2 x i64> %out
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}
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;
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; SUB
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;
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define <vscale x 16 x i8> @sub_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
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; CHECK-LABEL: sub_i8:
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; CHECK: movprfx z0.b, p0/z, z0.b
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; CHECK-NEXT: sub z0.b, p0/m, z0.b, z1.b
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; CHECK-NEXT: ret
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%a_z = select <vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> zeroinitializer
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%out = call <vscale x 16 x i8> @llvm.aarch64.sve.sub.nxv16i8(<vscale x 16 x i1> %pg,
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<vscale x 16 x i8> %a_z,
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<vscale x 16 x i8> %b)
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ret <vscale x 16 x i8> %out
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}
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define <vscale x 8 x i16> @sub_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
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; CHECK-LABEL: sub_i16:
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; CHECK: movprfx z0.h, p0/z, z0.h
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; CHECK-NEXT: sub z0.h, p0/m, z0.h, z1.h
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; CHECK-NEXT: ret
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%a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> zeroinitializer
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%out = call <vscale x 8 x i16> @llvm.aarch64.sve.sub.nxv8i16(<vscale x 8 x i1> %pg,
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<vscale x 8 x i16> %a_z,
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<vscale x 8 x i16> %b)
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ret <vscale x 8 x i16> %out
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}
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define <vscale x 4 x i32> @sub_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
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; CHECK-LABEL: sub_i32:
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; CHECK: movprfx z0.s, p0/z, z0.s
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; CHECK-NEXT: sub z0.s, p0/m, z0.s, z1.s
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; CHECK-NEXT: ret
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%a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> zeroinitializer
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%out = call <vscale x 4 x i32> @llvm.aarch64.sve.sub.nxv4i32(<vscale x 4 x i1> %pg,
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<vscale x 4 x i32> %a_z,
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<vscale x 4 x i32> %b)
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ret <vscale x 4 x i32> %out
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}
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define <vscale x 2 x i64> @sub_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
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; CHECK-LABEL: sub_i64:
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; CHECK: movprfx z0.d, p0/z, z0.d
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; CHECK-NEXT: sub z0.d, p0/m, z0.d, z1.d
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; CHECK-NEXT: ret
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%a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> zeroinitializer
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%out = call <vscale x 2 x i64> @llvm.aarch64.sve.sub.nxv2i64(<vscale x 2 x i1> %pg,
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<vscale x 2 x i64> %a_z,
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<vscale x 2 x i64> %b)
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ret <vscale x 2 x i64> %out
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}
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;
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; SUBR
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;
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define <vscale x 16 x i8> @subr_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
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; CHECK-LABEL: subr_i8:
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; CHECK: movprfx z0.b, p0/z, z0.b
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; CHECK-NEXT: subr z0.b, p0/m, z0.b, z1.b
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; CHECK-NEXT: ret
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%a_z = select <vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> zeroinitializer
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%out = call <vscale x 16 x i8> @llvm.aarch64.sve.subr.nxv16i8(<vscale x 16 x i1> %pg,
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<vscale x 16 x i8> %a_z,
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<vscale x 16 x i8> %b)
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ret <vscale x 16 x i8> %out
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}
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define <vscale x 8 x i16> @subr_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
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; CHECK-LABEL: subr_i16:
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; CHECK: movprfx z0.h, p0/z, z0.h
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; CHECK-NEXT: subr z0.h, p0/m, z0.h, z1.h
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; CHECK-NEXT: ret
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%a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> zeroinitializer
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%out = call <vscale x 8 x i16> @llvm.aarch64.sve.subr.nxv8i16(<vscale x 8 x i1> %pg,
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<vscale x 8 x i16> %a_z,
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<vscale x 8 x i16> %b)
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ret <vscale x 8 x i16> %out
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}
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define <vscale x 4 x i32> @subr_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
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; CHECK-LABEL: subr_i32:
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; CHECK: movprfx z0.s, p0/z, z0.s
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; CHECK-NEXT: subr z0.s, p0/m, z0.s, z1.s
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; CHECK-NEXT: ret
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%a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> zeroinitializer
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%out = call <vscale x 4 x i32> @llvm.aarch64.sve.subr.nxv4i32(<vscale x 4 x i1> %pg,
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<vscale x 4 x i32> %a_z,
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<vscale x 4 x i32> %b)
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ret <vscale x 4 x i32> %out
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}
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define <vscale x 2 x i64> @subr_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
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; CHECK-LABEL: subr_i64:
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; CHECK: movprfx z0.d, p0/z, z0.d
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; CHECK-NEXT: subr z0.d, p0/m, z0.d, z1.d
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; CHECK-NEXT: ret
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%a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> zeroinitializer
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%out = call <vscale x 2 x i64> @llvm.aarch64.sve.subr.nxv2i64(<vscale x 2 x i1> %pg,
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<vscale x 2 x i64> %a_z,
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<vscale x 2 x i64> %b)
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ret <vscale x 2 x i64> %out
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}
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declare <vscale x 16 x i8> @llvm.aarch64.sve.add.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
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declare <vscale x 8 x i16> @llvm.aarch64.sve.add.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
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declare <vscale x 4 x i32> @llvm.aarch64.sve.add.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
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declare <vscale x 2 x i64> @llvm.aarch64.sve.add.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)
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declare <vscale x 16 x i8> @llvm.aarch64.sve.sub.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
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declare <vscale x 8 x i16> @llvm.aarch64.sve.sub.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
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declare <vscale x 4 x i32> @llvm.aarch64.sve.sub.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
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declare <vscale x 2 x i64> @llvm.aarch64.sve.sub.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)
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declare <vscale x 16 x i8> @llvm.aarch64.sve.subr.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
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declare <vscale x 8 x i16> @llvm.aarch64.sve.subr.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
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declare <vscale x 4 x i32> @llvm.aarch64.sve.subr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
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declare <vscale x 2 x i64> @llvm.aarch64.sve.subr.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)
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