forked from OSchip/llvm-project
[PowerPC] Follow-up to r318436 to get the missed CSE opportunities
The last of the three patches that https://reviews.llvm.org/D40348 was broken up into. Canonicalize the materialization of constants so that they are more likely to be CSE'd regardless of the bit-width of the use. If a constant can be materialized using PPC::LI, materialize it the same way always. For example: li 4, -1 li 4, 255 li 4, 65535 are equivalent if the uses only use the low byte. Canonicalize it to the first form. Differential Revision: https://reviews.llvm.org/D40348 llvm-svn: 320473
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@ -786,8 +786,10 @@ static SDNode *selectI64ImmDirect(SelectionDAG *CurDAG, const SDLoc &dl,
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// Simple value.
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// Simple value.
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if (isInt<16>(Imm)) {
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if (isInt<16>(Imm)) {
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uint64_t SextImm = SignExtend64(Lo, 16);
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SDValue SDImm = CurDAG->getTargetConstant(SextImm, dl, MVT::i64);
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// Just the Lo bits.
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// Just the Lo bits.
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Result = CurDAG->getMachineNode(PPC::LI8, dl, MVT::i64, getI32Imm(Lo));
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Result = CurDAG->getMachineNode(PPC::LI8, dl, MVT::i64, SDImm);
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} else if (Lo) {
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} else if (Lo) {
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// Handle the Hi bits.
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// Handle the Hi bits.
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unsigned OpC = Hi ? PPC::LIS8 : PPC::LI8;
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unsigned OpC = Hi ? PPC::LIS8 : PPC::LI8;
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@ -892,12 +894,74 @@ static SDNode *selectI64Imm(SelectionDAG *CurDAG, const SDLoc &dl,
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getI32Imm(64 - RMin), getI32Imm(MaskEnd));
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getI32Imm(64 - RMin), getI32Imm(MaskEnd));
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}
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}
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static unsigned allUsesTruncate(SelectionDAG *CurDAG, SDNode *N) {
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unsigned MaxTruncation = 0;
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// Cannot use range-based for loop here as we need the actual use (i.e. we
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// need the operand number corresponding to the use). A range-based for
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// will unbox the use and provide an SDNode*.
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for (SDNode::use_iterator Use = N->use_begin(), UseEnd = N->use_end();
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Use != UseEnd; ++Use) {
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unsigned Opc =
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Use->isMachineOpcode() ? Use->getMachineOpcode() : Use->getOpcode();
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switch (Opc) {
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default: return 0;
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case ISD::TRUNCATE:
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if (Use->isMachineOpcode())
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return 0;
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MaxTruncation =
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std::max(MaxTruncation, Use->getValueType(0).getSizeInBits());
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continue;
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case ISD::STORE: {
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if (Use->isMachineOpcode())
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return 0;
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StoreSDNode *STN = cast<StoreSDNode>(*Use);
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unsigned MemVTSize = STN->getMemoryVT().getSizeInBits();
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if (MemVTSize == 64 || Use.getOperandNo() != 0)
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return 0;
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MaxTruncation = std::max(MaxTruncation, MemVTSize);
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continue;
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}
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case PPC::STW8:
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case PPC::STWX8:
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case PPC::STWU8:
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case PPC::STWUX8:
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if (Use.getOperandNo() != 0)
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return 0;
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MaxTruncation = std::max(MaxTruncation, 32u);
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continue;
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case PPC::STH8:
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case PPC::STHX8:
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case PPC::STHU8:
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case PPC::STHUX8:
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if (Use.getOperandNo() != 0)
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return 0;
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MaxTruncation = std::max(MaxTruncation, 16u);
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continue;
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case PPC::STB8:
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case PPC::STBX8:
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case PPC::STBU8:
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case PPC::STBUX8:
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if (Use.getOperandNo() != 0)
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return 0;
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MaxTruncation = std::max(MaxTruncation, 8u);
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continue;
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}
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}
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return MaxTruncation;
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}
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// Select a 64-bit constant.
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// Select a 64-bit constant.
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static SDNode *selectI64Imm(SelectionDAG *CurDAG, SDNode *N) {
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static SDNode *selectI64Imm(SelectionDAG *CurDAG, SDNode *N) {
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SDLoc dl(N);
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SDLoc dl(N);
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// Get 64 bit value.
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// Get 64 bit value.
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int64_t Imm = cast<ConstantSDNode>(N)->getZExtValue();
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int64_t Imm = cast<ConstantSDNode>(N)->getZExtValue();
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if (unsigned MinSize = allUsesTruncate(CurDAG, N)) {
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uint64_t SextImm = SignExtend64(Imm, MinSize);
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SDValue SDImm = CurDAG->getTargetConstant(SextImm, dl, MVT::i64);
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if (isInt<16>(SextImm))
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return CurDAG->getMachineNode(PPC::LI8, dl, MVT::i64, SDImm);
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}
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return selectI64Imm(CurDAG, dl, Imm);
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return selectI64Imm(CurDAG, dl, Imm);
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}
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}
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@ -1,5 +1,13 @@
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; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -verify-machineinstrs | FileCheck %s
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; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -verify-machineinstrs | FileCheck %s
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@CVal = external local_unnamed_addr global i8, align 1
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@SVal = external local_unnamed_addr global i16, align 2
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@IVal = external local_unnamed_addr global i32, align 4
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@LVal = external local_unnamed_addr global i64, align 8
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@USVal = external local_unnamed_addr global i16, align 2
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@arr = external local_unnamed_addr global i64*, align 8
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@arri = external local_unnamed_addr global i32*, align 8
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; Test the same constant can be used by different stores.
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; Test the same constant can be used by different stores.
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%struct.S = type { i64, i8, i16, i32 }
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%struct.S = type { i64, i8, i16, i32 }
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@ -42,3 +50,142 @@ define void @bar(%struct.S* %p) {
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; CHECK: stb 4, 8(3)
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; CHECK: stb 4, 8(3)
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}
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}
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; Function Attrs: norecurse nounwind
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define void @setSmallNeg() {
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entry:
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store i8 -7, i8* @CVal, align 1
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store i16 -7, i16* @SVal, align 2
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store i32 -7, i32* @IVal, align 4
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store i64 -7, i64* @LVal, align 8
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ret void
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; CHECK-LABEL: setSmallNeg
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; CHECK: li 7, -7
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; CHECK-DAG: stb 7,
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; CHECK-DAG: sth 7,
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; CHECK-DAG: stw 7,
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; CHECK-DAG: std 7,
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}
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; Function Attrs: norecurse nounwind
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define void @setSmallPos() {
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entry:
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store i8 8, i8* @CVal, align 1
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store i16 8, i16* @SVal, align 2
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store i32 8, i32* @IVal, align 4
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store i64 8, i64* @LVal, align 8
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ret void
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; CHECK-LABEL: setSmallPos
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; CHECK: li 7, 8
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; CHECK-DAG: stb 7,
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; CHECK-DAG: sth 7,
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; CHECK-DAG: stw 7,
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; CHECK-DAG: std 7,
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}
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; Function Attrs: norecurse nounwind
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define void @setMaxNeg() {
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entry:
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store i16 -32768, i16* @SVal, align 2
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store i32 -32768, i32* @IVal, align 4
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store i64 -32768, i64* @LVal, align 8
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ret void
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; CHECK-LABEL: setMaxNeg
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; CHECK: li 6, -32768
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; CHECK-DAG: sth 6,
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; CHECK-DAG: stw 6,
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; CHECK-DAG: std 6,
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}
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; Function Attrs: norecurse nounwind
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define void @setMaxPos() {
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entry:
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store i16 32767, i16* @SVal, align 2
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store i32 32767, i32* @IVal, align 4
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store i64 32767, i64* @LVal, align 8
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ret void
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; CHECK-LABEL: setMaxPos
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; CHECK: li 6, 32767
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; CHECK-DAG: sth 6,
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; CHECK-DAG: stw 6,
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; CHECK-DAG: std 6,
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}
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; Function Attrs: norecurse nounwind
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define void @setExcessiveNeg() {
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entry:
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store i32 -32769, i32* @IVal, align 4
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store i64 -32769, i64* @LVal, align 8
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ret void
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; CHECK-LABEL: setExcessiveNeg
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; CHECK: lis 5, -1
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; CHECK: ori 5, 5, 32767
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; CHECK-DAG: stw 5,
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; CHECK-DAG: std 5,
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}
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; Function Attrs: norecurse nounwind
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define void @setExcessivePos() {
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entry:
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store i16 -32768, i16* @USVal, align 2
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store i32 32768, i32* @IVal, align 4
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store i64 32768, i64* @LVal, align 8
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ret void
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; CHECK-LABEL: setExcessivePos
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; CHECK: li 6, 0
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; CHECK: ori 6, 6, 32768
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; CHECK-DAG: sth 6,
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; CHECK-DAG: stw 6,
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; CHECK-DAG: std 6,
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}
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define void @SetArr(i32 signext %Len) {
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entry:
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%cmp7 = icmp sgt i32 %Len, 0
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br i1 %cmp7, label %for.body.lr.ph, label %for.cond.cleanup
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for.body.lr.ph: ; preds = %entry
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%0 = load i64*, i64** @arr, align 8
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%1 = load i32*, i32** @arri, align 8
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%wide.trip.count = zext i32 %Len to i64
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br label %for.body
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for.cond.cleanup: ; preds = %for.body, %entry
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ret void
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for.body: ; preds = %for.body, %for.body.lr.ph
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%indvars.iv = phi i64 [ 0, %for.body.lr.ph ], [ %indvars.iv.next, %for.body ]
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%arrayidx = getelementptr inbounds i64, i64* %0, i64 %indvars.iv
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store i64 -7, i64* %arrayidx, align 8
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%arrayidx2 = getelementptr inbounds i32, i32* %1, i64 %indvars.iv
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store i32 -7, i32* %arrayidx2, align 4
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%exitcond = icmp eq i64 %indvars.iv.next, %wide.trip.count
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br i1 %exitcond, label %for.cond.cleanup, label %for.body
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; CHECK-LABEL: SetArr
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; CHECK: li 5, -7
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; CHECK: stdu 5, 8(3)
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; CHECK: stwu 5, 4(4)
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}
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define void @setSameValDiffSizeCI() {
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entry:
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store i32 255, i32* @IVal, align 4
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store i8 -1, i8* @CVal, align 1
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ret void
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; CHECK-LABEL: setSameValDiffSizeCI
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; CHECK: li 5, 255
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; CHECK-DAG: stb 5,
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; CHECK-DAG: stw 5,
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}
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define void @setSameValDiffSizeSI() {
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entry:
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store i32 65535, i32* @IVal, align 4
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store i16 -1, i16* @SVal, align 2
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ret void
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; CHECK-LABEL: setSameValDiffSizeSI
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; CHECK: li 5, 0
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; CHECK: ori 5, 5, 65535
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; CHECK-DAG: sth 5,
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; CHECK-DAG: stw 5,
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}
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store i8 %conv3, i8* @glob
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store i8 %conv3, i8* @glob
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ret void
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ret void
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; CHECK-LABEL: @test_igeuc_sext_z_store
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; CHECK-LABEL: @test_igeuc_sext_z_store
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; CHECK: li [[REG1:r[0-9]+]], 255
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; CHECK: li [[REG1:r[0-9]+]], -1
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; CHECK: stb [[REG1]]
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; CHECK: stb [[REG1]]
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; CHECK: blr
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; CHECK: blr
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}
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}
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@ -105,9 +105,8 @@ entry:
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store i16 %conv3, i16* @glob
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store i16 %conv3, i16* @glob
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ret void
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ret void
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; CHECK-LABEL: @test_igeus_sext_z_store
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; CHECK-LABEL: @test_igeus_sext_z_store
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; CHECK: li [[REG1:r[0-9]+]], 0
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; CHECK: li [[REG1:r[0-9]+]], -1
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; CHECK: ori [[REG2:r[0-9]+]], [[REG1]], 65535
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; CHECK: sth [[REG1]]
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; CHECK: sth [[REG2]]
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; CHECK: blr
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; CHECK: blr
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}
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}
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@ -105,7 +105,7 @@ entry:
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store i8 %conv1, i8* @glob
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store i8 %conv1, i8* @glob
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ret void
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ret void
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; CHECK-LABEL: @test_llgeuc_sext_z_store
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; CHECK-LABEL: @test_llgeuc_sext_z_store
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; CHECK: li [[REG1:r[0-9]+]], 255
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; CHECK: li [[REG1:r[0-9]+]], -1
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; CHECK: stb [[REG1]]
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; CHECK: stb [[REG1]]
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; CHECK: blr
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; CHECK: blr
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}
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}
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@ -105,9 +105,8 @@ entry:
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store i16 %conv1, i16* @glob
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store i16 %conv1, i16* @glob
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ret void
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ret void
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; CHECK-LABEL: @test_llgeus_sext_z_store
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; CHECK-LABEL: @test_llgeus_sext_z_store
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; CHECK: li [[REG1:r[0-9]+]], 0
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; CHECK: li [[REG1:r[0-9]+]], -1
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; CHECK: ori [[REG2:r[0-9]+]], [[REG1]], 65535
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; CHECK: sth [[REG1]]
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; CHECK: sth [[REG2]]
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; CHECK: blr
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; CHECK: blr
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}
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}
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