From b0742bf30d53c9faaa45ff7e4a5ce787c6b8f09a Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Thu, 14 Jun 2018 15:40:29 +0000 Subject: [PATCH] [X86] Disable load unfolding for a bunch of instruction where unfolding would increase the size of the load. Found by an audit of the manual table vs the autogenerated table. llvm-svn: 334726 --- llvm/lib/Target/X86/X86InstrInfo.cpp | 32 ++++++++++++++-------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp index 27da90d80e75..7e3f89c7c191 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.cpp +++ b/llvm/lib/Target/X86/X86InstrInfo.cpp @@ -841,8 +841,8 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI) { X86::VFRCZPDYrr, X86::VFRCZPDYrm, 0 }, { X86::VFRCZPSrr, X86::VFRCZPSrm, 0 }, { X86::VFRCZPSYrr, X86::VFRCZPSYrm, 0 }, - { X86::VFRCZSDrr, X86::VFRCZSDrm, 0 }, - { X86::VFRCZSSrr, X86::VFRCZSSrm, 0 }, + { X86::VFRCZSDrr, X86::VFRCZSDrm, TB_NO_REVERSE }, + { X86::VFRCZSSrr, X86::VFRCZSSrm, TB_NO_REVERSE }, { X86::VPHADDBDrr, X86::VPHADDBDrm, 0 }, { X86::VPHADDBQrr, X86::VPHADDBQrm, 0 }, { X86::VPHADDBWrr, X86::VPHADDBWrm, 0 }, @@ -1310,10 +1310,10 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI) { X86::PHSUBDrr, X86::PHSUBDrm, TB_ALIGN_16 }, { X86::PHSUBSWrr, X86::PHSUBSWrm, TB_ALIGN_16 }, { X86::PHSUBWrr, X86::PHSUBWrm, TB_ALIGN_16 }, - { X86::PINSRBrr, X86::PINSRBrm, 0 }, + { X86::PINSRBrr, X86::PINSRBrm, TB_NO_REVERSE }, { X86::PINSRDrr, X86::PINSRDrm, 0 }, { X86::PINSRQrr, X86::PINSRQrm, 0 }, - { X86::PINSRWrr, X86::PINSRWrm, 0 }, + { X86::PINSRWrr, X86::PINSRWrm, TB_NO_REVERSE }, { X86::PMADDUBSWrr, X86::PMADDUBSWrm, TB_ALIGN_16 }, { X86::PMADDWDrr, X86::PMADDWDrm, TB_ALIGN_16 }, { X86::PMAXSBrr, X86::PMAXSBrm, TB_ALIGN_16 }, @@ -1430,7 +1430,7 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI) { X86::MMX_PHSUBDrr, X86::MMX_PHSUBDrm, 0 }, { X86::MMX_PHSUBSWrr, X86::MMX_PHSUBSWrm, 0 }, { X86::MMX_PHSUBWrr, X86::MMX_PHSUBWrm, 0 }, - { X86::MMX_PINSRWrr, X86::MMX_PINSRWrm, 0 }, + { X86::MMX_PINSRWrr, X86::MMX_PINSRWrm, TB_NO_REVERSE }, { X86::MMX_PMADDUBSWrr, X86::MMX_PMADDUBSWrm, 0 }, { X86::MMX_PMADDWDirr, X86::MMX_PMADDWDirm, 0 }, { X86::MMX_PMAXSWirr, X86::MMX_PMAXSWirm, 0 }, @@ -1467,9 +1467,9 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI) { X86::MMX_PUNPCKHBWirr, X86::MMX_PUNPCKHBWirm, 0 }, { X86::MMX_PUNPCKHDQirr, X86::MMX_PUNPCKHDQirm, 0 }, { X86::MMX_PUNPCKHWDirr, X86::MMX_PUNPCKHWDirm, 0 }, - { X86::MMX_PUNPCKLBWirr, X86::MMX_PUNPCKLBWirm, 0 }, - { X86::MMX_PUNPCKLDQirr, X86::MMX_PUNPCKLDQirm, 0 }, - { X86::MMX_PUNPCKLWDirr, X86::MMX_PUNPCKLWDirm, 0 }, + { X86::MMX_PUNPCKLBWirr, X86::MMX_PUNPCKLBWirm, TB_NO_REVERSE }, + { X86::MMX_PUNPCKLDQirr, X86::MMX_PUNPCKLDQirm, TB_NO_REVERSE }, + { X86::MMX_PUNPCKLWDirr, X86::MMX_PUNPCKLWDirm, TB_NO_REVERSE }, { X86::MMX_PXORirr, X86::MMX_PXORirm, 0 }, // 3DNow! version of foldable instructions @@ -1600,10 +1600,10 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI) { X86::VPHSUBWrr, X86::VPHSUBWrm, 0 }, { X86::VPERMILPDrr, X86::VPERMILPDrm, 0 }, { X86::VPERMILPSrr, X86::VPERMILPSrm, 0 }, - { X86::VPINSRBrr, X86::VPINSRBrm, 0 }, + { X86::VPINSRBrr, X86::VPINSRBrm, TB_NO_REVERSE }, { X86::VPINSRDrr, X86::VPINSRDrm, 0 }, { X86::VPINSRQrr, X86::VPINSRQrm, 0 }, - { X86::VPINSRWrr, X86::VPINSRWrm, 0 }, + { X86::VPINSRWrr, X86::VPINSRWrm, TB_NO_REVERSE }, { X86::VPMADDUBSWrr, X86::VPMADDUBSWrm, 0 }, { X86::VPMADDWDrr, X86::VPMADDWDrm, 0 }, { X86::VPMAXSBrr, X86::VPMAXSBrm, 0 }, @@ -2040,10 +2040,10 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI) { X86::VPERMPSZrr, X86::VPERMPSZrm, 0 }, { X86::VPERMQZrr, X86::VPERMQZrm, 0 }, { X86::VPERMWZrr, X86::VPERMWZrm, 0 }, - { X86::VPINSRBZrr, X86::VPINSRBZrm, 0 }, + { X86::VPINSRBZrr, X86::VPINSRBZrm, TB_NO_REVERSE }, { X86::VPINSRDZrr, X86::VPINSRDZrm, 0 }, { X86::VPINSRQZrr, X86::VPINSRQZrm, 0 }, - { X86::VPINSRWZrr, X86::VPINSRWZrm, 0 }, + { X86::VPINSRWZrr, X86::VPINSRWZrm, TB_NO_REVERSE }, { X86::VPMADDUBSWZrr, X86::VPMADDUBSWZrm, 0 }, { X86::VPMADDWDZrr, X86::VPMADDWDZrm, 0 }, { X86::VPMAXSBZrr, X86::VPMAXSBZrm, 0 }, @@ -3310,14 +3310,14 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI) { X86::VMAXCPSZrrk, X86::VMAXCPSZrmk, 0 }, { X86::VMAXPDZrrk, X86::VMAXPDZrmk, 0 }, { X86::VMAXPSZrrk, X86::VMAXPSZrmk, 0 }, - { X86::VMAXSDZrr_Intk, X86::VMAXSDZrm_Intk, 0 }, - { X86::VMAXSSZrr_Intk, X86::VMAXSSZrm_Intk, 0 }, + { X86::VMAXSDZrr_Intk, X86::VMAXSDZrm_Intk, TB_NO_REVERSE }, + { X86::VMAXSSZrr_Intk, X86::VMAXSSZrm_Intk, TB_NO_REVERSE }, { X86::VMINCPDZrrk, X86::VMINCPDZrmk, 0 }, { X86::VMINCPSZrrk, X86::VMINCPSZrmk, 0 }, { X86::VMINPDZrrk, X86::VMINPDZrmk, 0 }, { X86::VMINPSZrrk, X86::VMINPSZrmk, 0 }, - { X86::VMINSDZrr_Intk, X86::VMINSDZrm_Intk, 0 }, - { X86::VMINSSZrr_Intk, X86::VMINSSZrm_Intk, 0 }, + { X86::VMINSDZrr_Intk, X86::VMINSDZrm_Intk, TB_NO_REVERSE }, + { X86::VMINSSZrr_Intk, X86::VMINSSZrm_Intk, TB_NO_REVERSE }, { X86::VMULPDZrrk, X86::VMULPDZrmk, 0 }, { X86::VMULPSZrrk, X86::VMULPSZrmk, 0 }, { X86::VMULSDZrr_Intk, X86::VMULSDZrm_Intk, TB_NO_REVERSE },