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Make i64=expand_vector_elt(v2i64) work in 32-bit mode. 

llvm-svn: 43535
This commit is contained in:
Dale Johannesen 2007-10-31 00:32:36 +00:00
parent ca5338196f
commit b066c1f216
2 changed files with 7 additions and 1 deletions
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5
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
View File

@ -5299,6 +5299,11 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
#endif
assert(0 && "Do not know how to expand this operator!");
abort();
case ISD::EXTRACT_VECTOR_ELT:
assert(VT==MVT::i64 && "Do not know how to expand this operator!");
// ExpandEXTRACT_VECTOR_ELT tolerates invalid result types.
Lo = ExpandEXTRACT_VECTOR_ELT(Op);
return ExpandOp(Lo, Lo, Hi);
case ISD::UNDEF:
NVT = TLI.getTypeToExpandTo(VT);
Lo = DAG.getNode(ISD::UNDEF, NVT);

3
llvm/lib/Target/X86/X86ISelLowering.cpp
View File

@ -608,7 +608,8 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
if (Subtarget->is64Bit())
setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
// Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) {