forked from OSchip/llvm-project
Inline assembly support for Blackfin.
We use the same constraints as GCC, including those that are slightly insane for inline assembler. llvm-svn: 77899
This commit is contained in:
Jakob Stoklund Olesen
parent
526e803f6a
commit
b052972a58
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@ -498,34 +498,104 @@ unsigned BlackfinTargetLowering::getFunctionAlignment(const Function *F) const {
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/// constraint it is for this target.
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BlackfinTargetLowering::ConstraintType
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BlackfinTargetLowering::getConstraintType(const std::string &Constraint) const {
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if (Constraint.size() == 1) {
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switch (Constraint[0]) {
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default: break;
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case 'r': return C_RegisterClass;
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}
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if (Constraint.size() != 1)
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return TargetLowering::getConstraintType(Constraint);
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switch (Constraint[0]) {
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// Standard constraints
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case 'r':
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return C_RegisterClass;
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// Blackfin-specific constraints
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case 'a':
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case 'd':
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case 'z':
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case 'D':
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case 'W':
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case 'e':
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case 'b':
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case 'v':
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case 'f':
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case 'c':
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case 't':
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case 'u':
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case 'k':
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case 'x':
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case 'y':
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case 'w':
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return C_RegisterClass;
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case 'A':
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case 'B':
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case 'C':
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case 'Z':
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case 'Y':
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return C_Register;
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}
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// Not implemented: q0-q7, qA. Use {R2} etc instead
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return TargetLowering::getConstraintType(Constraint);
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}
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/// getRegForInlineAsmConstraint - Return register no and class for a C_Register
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/// constraint.
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std::pair<unsigned, const TargetRegisterClass*> BlackfinTargetLowering::
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getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const {
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if (Constraint.size() == 1) {
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switch (Constraint[0]) {
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case 'r':
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return std::make_pair(0U, BF::DRegisterClass);
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}
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typedef std::pair<unsigned, const TargetRegisterClass*> Pair;
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using namespace BF;
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if (Constraint.size() != 1)
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return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
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switch (Constraint[0]) {
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// Standard constraints
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case 'r':
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return Pair(0U, VT == MVT::i16 ? D16RegisterClass : DPRegisterClass);
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// Blackfin-specific constraints
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case 'a': return Pair(0U, PRegisterClass);
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case 'd': return Pair(0U, DRegisterClass);
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case 'e': return Pair(0U, AccuRegisterClass);
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case 'A': return Pair(A0, AccuRegisterClass);
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case 'B': return Pair(A1, AccuRegisterClass);
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case 'b': return Pair(0U, IRegisterClass);
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case 'v': return Pair(0U, BRegisterClass);
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case 'f': return Pair(0U, MRegisterClass);
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case 'C': return Pair(CC, JustCCRegisterClass);
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case 'x': return Pair(0U, GRRegisterClass);
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case 'w': return Pair(0U, ALLRegisterClass);
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case 'Z': return Pair(P3, PRegisterClass);
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case 'Y': return Pair(P1, PRegisterClass);
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}
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// Not implemented: q0-q7, qA. Use {R2} etc instead.
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// Constraints z, D, W, c, t, u, k, and y use non-existing classes, defer to
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// getRegClassForInlineAsmConstraint()
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return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
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}
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std::vector<unsigned> BlackfinTargetLowering::
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getRegClassForInlineAsmConstraint(const std::string &Constraint,
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MVT VT) const {
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getRegClassForInlineAsmConstraint(const std::string &Constraint, MVT VT) const {
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using namespace BF;
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if (Constraint.size() != 1)
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return std::vector<unsigned>();
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switch (Constraint[0]) {
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case 'z': return make_vector<unsigned>(P0, P1, P2, 0);
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case 'D': return make_vector<unsigned>(R0, R2, R4, R6, 0);
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case 'W': return make_vector<unsigned>(R1, R3, R5, R7, 0);
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case 'c': return make_vector<unsigned>(I0, I1, I2, I3,
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B0, B1, B2, B3,
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L0, L1, L2, L3, 0);
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case 't': return make_vector<unsigned>(LT0, LT1, 0);
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case 'u': return make_vector<unsigned>(LB0, LB1, 0);
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case 'k': return make_vector<unsigned>(LC0, LC1, 0);
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case 'y': return make_vector<unsigned>(RETS, RETN, RETI, RETX, RETE,
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ASTAT, SEQSTAT, USP, 0);
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}
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return std::vector<unsigned>();
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}
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@ -281,6 +281,8 @@ def P : RegisterClass<"BF", [i32], 32, [P0, P1, P2, P3, P4, P5, FP, SP]> {
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def I : RegisterClass<"BF", [i32], 32, [I0, I1, I2, I3]>;
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def M : RegisterClass<"BF", [i32], 32, [M0, M1, M2, M3]>;
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def B : RegisterClass<"BF", [i32], 32, [B0, B1, B2, B3]>;
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def L : RegisterClass<"BF", [i32], 32, [L0, L1, L2, L3]>;
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def DP : RegisterClass<"BF", [i32], 32,
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[R0, R1, R2, R3, R4, R5, R6, R7,
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@ -378,3 +380,6 @@ def AnyCC : RegisterClass<"BF", [i32], 8, [CC, NCC]> {
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def StatBit : RegisterClass<"BF", [i1], 8,
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[AZ, AN, CC, AQ, AC0, AC1, AV0, AV0S, AV1, AV1S, V, VS]>;
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}
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// Should be i40, but that isn't defined. It is not a legal type yet anyway.
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def Accu : RegisterClass<"BF", [i64], 64, [A0, A1]>;
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@ -41,6 +41,56 @@ should keep track of:
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It's a hack combining two instructions by concatenation.
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* Inline Assembly
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These are the GCC constraints from bfin/constraints.md:
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| Code | Register class | LLVM |
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|-------+-------------------------------------------+------|
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| a | P | C |
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| d | D | C |
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| z | Call clobbered P (P0, P1, P2) | X |
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| D | EvenD | X |
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| W | OddD | X |
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| e | Accu | C |
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| A | A0 | S |
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| B | A1 | S |
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| b | I | C |
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| v | B | C |
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| f | M | C |
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| c | Circular I, B, L | X |
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| C | JustCC | S |
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| t | LoopTop | X |
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| u | LoopBottom | X |
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| k | LoopCount | X |
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| x | GR | C |
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| y | RET*, ASTAT, SEQSTAT, USP | X |
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| w | ALL | C |
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| Z | The FD-PIC GOT pointer (P3) | S |
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| Y | The FD-PIC function pointer register (P1) | S |
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| q0-q7 | R0-R7 individually | |
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| qA | P0 | |
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|-------+-------------------------------------------+------|
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| Code | Constant | |
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|-------+-------------------------------------------+------|
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| J | 1<<N, N<32 | |
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| Ks3 | imm3 | |
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| Ku3 | uimm3 | |
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| Ks4 | imm4 | |
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| Ku4 | uimm4 | |
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| Ks5 | imm5 | |
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| Ku5 | uimm5 | |
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| Ks7 | imm7 | |
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| KN7 | -imm7 | |
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| Ksh | imm16 | |
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| Kuh | uimm16 | |
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| L | ~(1<<N) | |
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| M1 | 0xff | |
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| M2 | 0xffff | |
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| P0-P4 | 0-4 | |
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| PA | Macflag, not M | |
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| PB | Macflag, only M | |
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| Q | Symbol | |
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** TODO Support all register classes
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* DAG combiner
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** Create test case for each Illegal SETCC case
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@ -0,0 +1,38 @@
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; RUN: llvm-as < %s | llc -march=bfin | FileCheck %s
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; Standard "r"
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; CHECK: r0 = r0 + r1;
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define i32 @add_r(i32 %A, i32 %B) {
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%R = call i32 asm "$0 = $1 + $2;", "=r,r,r"( i32 %A, i32 %B ) nounwind
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ret i32 %R
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}
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; Target "d"
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; CHECK: r0 = r0 - r1;
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define i32 @add_d(i32 %A, i32 %B) {
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%R = call i32 asm "$0 = $1 - $2;", "=d,d,d"( i32 %A, i32 %B ) nounwind
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ret i32 %R
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}
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; Target "a" for P-regs
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; CHECK: p0 = (p0 + p1) << 1;
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define i32 @add_a(i32 %A, i32 %B) {
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%R = call i32 asm "$0 = ($1 + $2) << 1;", "=a,a,a"( i32 %A, i32 %B ) nounwind
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ret i32 %R
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}
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; Target "z" for P0, P1, P2. This is not a real regclass
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; CHECK: p0 = (p0 + p1) << 2;
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define i32 @add_Z(i32 %A, i32 %B) {
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%R = call i32 asm "$0 = ($1 + $2) << 2;", "=z,z,z"( i32 %A, i32 %B ) nounwind
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ret i32 %R
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}
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; Target "C" for CC. This is a single register
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; CHECK: cc = p0 < p1;
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; CHECK: r0 = cc;
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define i32 @add_C(i32 %A, i32 %B) {
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%R = call i32 asm "$0 = $1 < $2;", "=C,z,z"( i32 %A, i32 %B ) nounwind
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ret i32 %R
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}
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