forked from OSchip/llvm-project
Mips specific inline asm operand modifier 'D'
Modifier 'D' is to use the second word of a double integer. We had previously implemented the pure register varient of the modifier and this patch implements the memory reference. #include "stdio.h" int b[8] = {0,1,2,3,4,5,6,7}; void main() { int i; // The first word. Notice, no 'D' {asm ( "lw %0,%1;" : "=r" (i) : "m" (*(b+4)) );} printf("%d\n",i); // The second word {asm ( "lw %0,%D1;" : "=r" (i) : "m" (*(b+4)) );} printf("%d\n",i); } llvm-svn: 179135
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@ -423,12 +423,18 @@ bool MipsAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
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unsigned OpNum, unsigned AsmVariant,
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const char *ExtraCode,
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raw_ostream &O) {
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if (ExtraCode && ExtraCode[0])
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return true; // Unknown modifier.
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int Offset = 0;
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// Currently we are expecting either no ExtraCode or 'D'
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if (ExtraCode) {
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if (ExtraCode[0] == 'D')
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Offset = 4;
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else
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return true; // Unknown modifier.
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}
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const MachineOperand &MO = MI->getOperand(OpNum);
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assert(MO.isReg() && "unexpected inline asm memory operand");
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O << "0($" << MipsInstPrinter::getRegisterName(MO.getReg()) << ")";
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O << Offset << "($" << MipsInstPrinter::getRegisterName(MO.getReg()) << ")";
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return false;
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}
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@ -1,5 +1,6 @@
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; RUN: llc -march=mipsel < %s | FileCheck %s
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; Simple memory
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@g1 = external global i32
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define i32 @f1(i32 %x) nounwind {
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@ -21,3 +22,19 @@ entry:
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ret i32 %0
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}
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; "D": Second word of double word. This works for any memory element.
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; CHECK: #APP
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; CHECK-NEXT: lw ${{[0-9]+}},4(${{[0-9]+}});
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; CHECK-NEXT: #NO_APP
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@b = common global [20 x i32] zeroinitializer, align 4
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define void @main() #0 {
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entry:
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tail call void asm sideeffect " lw $0,${1:D};", "r,*m,~{$11}"(i32 undef, i32* getelementptr inbounds ([20 x i32]* @b, i32 0, i32 3)) #1
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ret void
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}
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attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
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attributes #1 = { nounwind }
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