forked from OSchip/llvm-project
ARM: use natural LLVM IR for vshll instructions
Similarly to the vshrn instructions, these are simple zext/sext + trunc operations. Using normal LLVM IR should allow for better code, and more sharing with the AArch64 backend. llvm-svn: 201093
This commit is contained in:
Tim Northover
parent
78c135942d
commit
b0430415e6
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@ -287,8 +287,6 @@ def int_arm_neon_vpminu : Neon_2Arg_Intrinsic;
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// Vector Shift.
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def int_arm_neon_vshifts : Neon_2Arg_Intrinsic;
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def int_arm_neon_vshiftu : Neon_2Arg_Intrinsic;
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def int_arm_neon_vshiftls : Neon_2Arg_Long_Intrinsic;
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def int_arm_neon_vshiftlu : Neon_2Arg_Long_Intrinsic;
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// Vector Rounding Shift.
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def int_arm_neon_vrshifts : Neon_2Arg_Intrinsic;
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@ -1078,9 +1078,6 @@ const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
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case ARMISD::VSHL: return "ARMISD::VSHL";
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case ARMISD::VSHRs: return "ARMISD::VSHRs";
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case ARMISD::VSHRu: return "ARMISD::VSHRu";
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case ARMISD::VSHLLs: return "ARMISD::VSHLLs";
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case ARMISD::VSHLLu: return "ARMISD::VSHLLu";
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case ARMISD::VSHLLi: return "ARMISD::VSHLLi";
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case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
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case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
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case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
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@ -9714,8 +9711,6 @@ static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
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// loads from a constant pool.
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case Intrinsic::arm_neon_vshifts:
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case Intrinsic::arm_neon_vshiftu:
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case Intrinsic::arm_neon_vshiftls:
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case Intrinsic::arm_neon_vshiftlu:
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case Intrinsic::arm_neon_vrshifts:
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case Intrinsic::arm_neon_vrshiftu:
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case Intrinsic::arm_neon_vrshiftn:
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@ -9746,12 +9741,6 @@ static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
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}
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return SDValue();
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case Intrinsic::arm_neon_vshiftls:
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case Intrinsic::arm_neon_vshiftlu:
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if (isVShiftLImm(N->getOperand(2), VT, true, Cnt))
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break;
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llvm_unreachable("invalid shift count for vshll intrinsic");
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case Intrinsic::arm_neon_vrshifts:
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case Intrinsic::arm_neon_vrshiftu:
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if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
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@ -9791,14 +9780,6 @@ static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
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case Intrinsic::arm_neon_vshiftu:
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// Opcode already set above.
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break;
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case Intrinsic::arm_neon_vshiftls:
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case Intrinsic::arm_neon_vshiftlu:
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if (Cnt == VT.getVectorElementType().getSizeInBits())
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VShiftOpc = ARMISD::VSHLLi;
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else
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VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ?
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ARMISD::VSHLLs : ARMISD::VSHLLu);
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break;
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case Intrinsic::arm_neon_vrshifts:
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VShiftOpc = ARMISD::VRSHRs; break;
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case Intrinsic::arm_neon_vrshiftu:
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@ -113,9 +113,6 @@ namespace llvm {
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VSHL, // ...left
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VSHRs, // ...right (signed)
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VSHRu, // ...right (unsigned)
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VSHLLs, // ...left long (signed)
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VSHLLu, // ...left long (unsigned)
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VSHLLi, // ...left long (with maximum shift count)
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// Vector rounding shift by immediate:
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VRSHRs, // ...right (signed)
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@ -466,9 +466,6 @@ def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
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def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
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def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
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def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
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def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
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def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
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def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
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def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
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def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
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@ -3038,12 +3035,12 @@ class N2VQSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
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// Long shift by immediate.
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class N2VLSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
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string OpcodeStr, string Dt,
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ValueType ResTy, ValueType OpTy, Operand ImmTy, SDNode OpNode>
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ValueType ResTy, ValueType OpTy, Operand ImmTy,
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SDPatternOperator OpNode>
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: N2VImm<op24, op23, op11_8, op7, op6, op4,
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(outs QPR:$Vd), (ins DPR:$Vm, ImmTy:$SIMM), N2RegVShLFrm,
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IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
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[(set QPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm),
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(i32 imm:$SIMM))))]>;
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[(set QPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm), ImmTy:$SIMM)))]>;
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// Narrow shift by immediate.
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class N2VNSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
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@ -3942,7 +3939,8 @@ multiclass N2VShInsR_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
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// Neon Shift Long operations,
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// element sizes of 8, 16, 32 bits:
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multiclass N2VLSh_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
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bit op4, string OpcodeStr, string Dt, SDNode OpNode> {
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bit op4, string OpcodeStr, string Dt,
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SDPatternOperator OpNode> {
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def v8i16 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
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OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, imm1_7, OpNode> {
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let Inst{21-19} = 0b001; // imm6 = 001xxx
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@ -4947,24 +4945,39 @@ defm VSHRu : N2VShR_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u", "VSHRu",
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NEONvshru>;
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// VSHLL : Vector Shift Left Long
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defm VSHLLs : N2VLSh_QHS<0, 1, 0b1010, 0, 0, 1, "vshll", "s", NEONvshlls>;
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defm VSHLLu : N2VLSh_QHS<1, 1, 0b1010, 0, 0, 1, "vshll", "u", NEONvshllu>;
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defm VSHLLs : N2VLSh_QHS<0, 1, 0b1010, 0, 0, 1, "vshll", "s",
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PatFrag<(ops node:$LHS, node:$RHS), (NEONvshl (sext node:$LHS), node:$RHS)>>;
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defm VSHLLu : N2VLSh_QHS<1, 1, 0b1010, 0, 0, 1, "vshll", "u",
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PatFrag<(ops node:$LHS, node:$RHS), (NEONvshl (zext node:$LHS), node:$RHS)>>;
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// VSHLL : Vector Shift Left Long (with maximum shift count)
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class N2VLShMax<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
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bit op6, bit op4, string OpcodeStr, string Dt, ValueType ResTy,
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ValueType OpTy, Operand ImmTy, SDNode OpNode>
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ValueType OpTy, Operand ImmTy>
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: N2VLSh<op24, op23, op11_8, op7, op6, op4, OpcodeStr, Dt,
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ResTy, OpTy, ImmTy, OpNode> {
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ResTy, OpTy, ImmTy, null_frag> {
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let Inst{21-16} = op21_16;
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let DecoderMethod = "DecodeVSHLMaxInstruction";
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}
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def VSHLLi8 : N2VLShMax<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll", "i8",
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v8i16, v8i8, imm8, NEONvshlli>;
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v8i16, v8i8, imm8>;
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def VSHLLi16 : N2VLShMax<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll", "i16",
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v4i32, v4i16, imm16, NEONvshlli>;
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v4i32, v4i16, imm16>;
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def VSHLLi32 : N2VLShMax<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll", "i32",
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v2i64, v2i32, imm32, NEONvshlli>;
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v2i64, v2i32, imm32>;
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def : Pat<(v8i16 (NEONvshl (zext (v8i8 DPR:$Rn)), (i32 8))),
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(VSHLLi8 DPR:$Rn, 8)>;
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def : Pat<(v4i32 (NEONvshl (zext (v4i16 DPR:$Rn)), (i32 16))),
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(VSHLLi16 DPR:$Rn, 16)>;
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def : Pat<(v2i64 (NEONvshl (zext (v2i32 DPR:$Rn)), (i32 32))),
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(VSHLLi32 DPR:$Rn, 32)>;
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def : Pat<(v8i16 (NEONvshl (sext (v8i8 DPR:$Rn)), (i32 8))),
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(VSHLLi8 DPR:$Rn, 8)>;
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def : Pat<(v4i32 (NEONvshl (sext (v4i16 DPR:$Rn)), (i32 16))),
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(VSHLLi16 DPR:$Rn, 16)>;
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def : Pat<(v2i64 (NEONvshl (sext (v2i32 DPR:$Rn)), (i32 32))),
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(VSHLLi32 DPR:$Rn, 32)>;
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// VSHRN : Vector Shift Right and Narrow
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defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VSHLiD, "vshrn", "i",
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@ -3,49 +3,55 @@
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define <8 x i16> @vshlls8(<8 x i8>* %A) nounwind {
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;CHECK-LABEL: vshlls8:
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;CHECK: vshll.s8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = call <8 x i16> @llvm.arm.neon.vshiftls.v8i16(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
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ret <8 x i16> %tmp2
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%tmp1 = load <8 x i8>* %A
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%sext = sext <8 x i8> %tmp1 to <8 x i16>
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%shift = shl <8 x i16> %sext, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
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ret <8 x i16> %shift
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}
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define <4 x i32> @vshlls16(<4 x i16>* %A) nounwind {
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;CHECK-LABEL: vshlls16:
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;CHECK: vshll.s16
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%tmp1 = load <4 x i16>* %A
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%tmp2 = call <4 x i32> @llvm.arm.neon.vshiftls.v4i32(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >)
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ret <4 x i32> %tmp2
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%tmp1 = load <4 x i16>* %A
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%sext = sext <4 x i16> %tmp1 to <4 x i32>
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%shift = shl <4 x i32> %sext, <i32 15, i32 15, i32 15, i32 15>
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ret <4 x i32> %shift
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}
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define <2 x i64> @vshlls32(<2 x i32>* %A) nounwind {
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;CHECK-LABEL: vshlls32:
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;CHECK: vshll.s32
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%tmp1 = load <2 x i32>* %A
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%tmp2 = call <2 x i64> @llvm.arm.neon.vshiftls.v2i64(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >)
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ret <2 x i64> %tmp2
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%tmp1 = load <2 x i32>* %A
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%sext = sext <2 x i32> %tmp1 to <2 x i64>
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%shift = shl <2 x i64> %sext, <i64 31, i64 31>
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ret <2 x i64> %shift
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}
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define <8 x i16> @vshllu8(<8 x i8>* %A) nounwind {
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;CHECK-LABEL: vshllu8:
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;CHECK: vshll.u8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = call <8 x i16> @llvm.arm.neon.vshiftlu.v8i16(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
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ret <8 x i16> %tmp2
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%tmp1 = load <8 x i8>* %A
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%zext = zext <8 x i8> %tmp1 to <8 x i16>
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%shift = shl <8 x i16> %zext, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
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ret <8 x i16> %shift
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}
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define <4 x i32> @vshllu16(<4 x i16>* %A) nounwind {
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;CHECK-LABEL: vshllu16:
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;CHECK: vshll.u16
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%tmp1 = load <4 x i16>* %A
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%tmp2 = call <4 x i32> @llvm.arm.neon.vshiftlu.v4i32(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >)
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ret <4 x i32> %tmp2
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%tmp1 = load <4 x i16>* %A
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%zext = zext <4 x i16> %tmp1 to <4 x i32>
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%shift = shl <4 x i32> %zext, <i32 15, i32 15, i32 15, i32 15>
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ret <4 x i32> %shift
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}
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define <2 x i64> @vshllu32(<2 x i32>* %A) nounwind {
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;CHECK-LABEL: vshllu32:
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;CHECK: vshll.u32
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%tmp1 = load <2 x i32>* %A
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%tmp2 = call <2 x i64> @llvm.arm.neon.vshiftlu.v2i64(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >)
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ret <2 x i64> %tmp2
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%tmp1 = load <2 x i32>* %A
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%zext = zext <2 x i32> %tmp1 to <2 x i64>
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%shift = shl <2 x i64> %zext, <i64 31, i64 31>
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ret <2 x i64> %shift
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}
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; The following tests use the maximum shift count, so the signedness is
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@ -53,31 +59,58 @@ define <2 x i64> @vshllu32(<2 x i32>* %A) nounwind {
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define <8 x i16> @vshlli8(<8 x i8>* %A) nounwind {
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;CHECK-LABEL: vshlli8:
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;CHECK: vshll.i8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = call <8 x i16> @llvm.arm.neon.vshiftls.v8i16(<8 x i8> %tmp1, <8 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >)
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ret <8 x i16> %tmp2
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%tmp1 = load <8 x i8>* %A
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%sext = sext <8 x i8> %tmp1 to <8 x i16>
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%shift = shl <8 x i16> %sext, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
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ret <8 x i16> %shift
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}
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define <4 x i32> @vshlli16(<4 x i16>* %A) nounwind {
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;CHECK-LABEL: vshlli16:
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;CHECK: vshll.i16
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%tmp1 = load <4 x i16>* %A
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%tmp2 = call <4 x i32> @llvm.arm.neon.vshiftlu.v4i32(<4 x i16> %tmp1, <4 x i16> < i16 16, i16 16, i16 16, i16 16 >)
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ret <4 x i32> %tmp2
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%tmp1 = load <4 x i16>* %A
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%zext = zext <4 x i16> %tmp1 to <4 x i32>
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%shift = shl <4 x i32> %zext, <i32 16, i32 16, i32 16, i32 16>
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ret <4 x i32> %shift
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}
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define <2 x i64> @vshlli32(<2 x i32>* %A) nounwind {
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;CHECK-LABEL: vshlli32:
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;CHECK: vshll.i32
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%tmp1 = load <2 x i32>* %A
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%tmp2 = call <2 x i64> @llvm.arm.neon.vshiftls.v2i64(<2 x i32> %tmp1, <2 x i32> < i32 32, i32 32 >)
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ret <2 x i64> %tmp2
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%tmp1 = load <2 x i32>* %A
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%zext = zext <2 x i32> %tmp1 to <2 x i64>
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%shift = shl <2 x i64> %zext, <i64 32, i64 32>
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ret <2 x i64> %shift
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}
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declare <8 x i16> @llvm.arm.neon.vshiftls.v8i16(<8 x i8>, <8 x i8>) nounwind readnone
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declare <4 x i32> @llvm.arm.neon.vshiftls.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
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declare <2 x i64> @llvm.arm.neon.vshiftls.v2i64(<2 x i32>, <2 x i32>) nounwind readnone
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; And these have a shift just out of range so separate vmovl and vshl
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; instructions are needed.
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define <8 x i16> @vshllu8_bad(<8 x i8>* %A) nounwind {
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; CHECK-LABEL: vshllu8_bad:
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; CHECK: vmovl.u8
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; CHECK: vshl.i16
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%tmp1 = load <8 x i8>* %A
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%zext = zext <8 x i8> %tmp1 to <8 x i16>
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%shift = shl <8 x i16> %zext, <i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9>
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ret <8 x i16> %shift
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}
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declare <8 x i16> @llvm.arm.neon.vshiftlu.v8i16(<8 x i8>, <8 x i8>) nounwind readnone
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declare <4 x i32> @llvm.arm.neon.vshiftlu.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
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declare <2 x i64> @llvm.arm.neon.vshiftlu.v2i64(<2 x i32>, <2 x i32>) nounwind readnone
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define <4 x i32> @vshlls16_bad(<4 x i16>* %A) nounwind {
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; CHECK-LABEL: vshlls16_bad:
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; CHECK: vmovl.s16
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; CHECK: vshl.i32
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%tmp1 = load <4 x i16>* %A
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%sext = sext <4 x i16> %tmp1 to <4 x i32>
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%shift = shl <4 x i32> %sext, <i32 17, i32 17, i32 17, i32 17>
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ret <4 x i32> %shift
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}
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define <2 x i64> @vshllu32_bad(<2 x i32>* %A) nounwind {
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; CHECK-LABEL: vshllu32_bad:
|
||||
; CHECK: vmovl.u32
|
||||
; CHECK: vshl.i64
|
||||
%tmp1 = load <2 x i32>* %A
|
||||
%zext = zext <2 x i32> %tmp1 to <2 x i64>
|
||||
%shift = shl <2 x i64> %zext, <i64 33, i64 33>
|
||||
ret <2 x i64> %shift
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue