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[AArch64] Improve the readability of the ld/st optimization pass. NFC. 

In this context, MI is an add/sub instruction not a loads/store.

llvm-svn: 248540
This commit is contained in:
Chad Rosier 2015-09-24 21:27:49 +00:00
parent 7d0c7255c5
commit b02f5a5a1f
1 changed files with 4 additions and 4 deletions
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8
llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
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@ -750,10 +750,10 @@ static bool isMatchingUpdateInsn(MachineInstr *MI, unsigned BaseReg,
break;
// If the instruction has the base register as source and dest and the
// immediate will fit in a signed 9-bit integer, then we have a match.
if (getLdStRegOp(MI).getReg() == BaseReg &&
getLdStBaseOp(MI).getReg() == BaseReg &&
getLdStOffsetOp(MI).getImm() <= 255 &&
getLdStOffsetOp(MI).getImm() >= -256) {
if (MI->getOperand(0).getReg() == BaseReg &&
MI->getOperand(1).getReg() == BaseReg &&
MI->getOperand(2).getImm() <= 255 &&
MI->getOperand(2).getImm() >= -256) {
// If we have a non-zero Offset, we check that it matches the amount
// we're adding to the register.
if (!Offset || Offset == MI->getOperand(2).getImm())