forked from OSchip/llvm-project
Fixed tryFoldToZero() for vector types that need expansion.
Summary: Moved the requirement for SelectionDAG::getConstant() to return legally typed nodes slightly earlier. There were two optional DAGCombine passes that were missed out and were required to produce type-legal DAGs. Simplified a code-path in tryFoldToZero() to use SelectionDAG::getConstant(). This provides support for both promoted and expanded vector types whereas the previous code only supported promoted vector types. Fixes a "Type for zero vector elements is not legal" assertion detected by an llvm-stress generated test. Reviewers: resistor CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D2251 llvm-svn: 195635
This commit is contained in:
Daniel Sanders
parent
5500f6163f
commit
b021c6fdbd
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@ -1635,19 +1635,8 @@ static SDValue tryFoldToZero(SDLoc DL, const TargetLowering &TLI, EVT VT,
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bool LegalOperations, bool LegalTypes) {
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if (!VT.isVector())
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return DAG.getConstant(0, VT);
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if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) {
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// Produce a vector of zeros.
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EVT ElemTy = VT.getVectorElementType();
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if (LegalTypes && TLI.getTypeAction(*DAG.getContext(), ElemTy) ==
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TargetLowering::TypePromoteInteger)
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ElemTy = TLI.getTypeToTransformTo(*DAG.getContext(), ElemTy);
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assert((!LegalTypes || TLI.isTypeLegal(ElemTy)) &&
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"Type for zero vector elements is not legal");
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SDValue El = DAG.getConstant(0, ElemTy);
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std::vector<SDValue> Ops(VT.getVectorNumElements(), El);
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return DAG.getNode(ISD::BUILD_VECTOR, DL, VT,
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&Ops[0], Ops.size());
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}
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if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT))
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return DAG.getConstant(0, VT);
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return SDValue();
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}
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@ -671,6 +671,8 @@ void SelectionDAGISel::CodeGenAndEmitDAG() {
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DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber
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<< " '" << BlockName << "'\n"; CurDAG->dump());
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CurDAG->NewNodesMustHaveLegalTypes = true;
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if (Changed) {
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if (ViewDAGCombineLT)
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CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
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@ -712,8 +714,6 @@ void SelectionDAGISel::CodeGenAndEmitDAG() {
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<< BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump());
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}
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CurDAG->NewNodesMustHaveLegalTypes = true;
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if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
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{
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@ -0,0 +1,143 @@
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; RUN: llc -march=mips < %s
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; RUN: llc -march=mips -mattr=+msa,+fp64 < %s
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; RUN: llc -march=mipsel < %s
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; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s
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; This test originally failed for MSA with a
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; "Type for zero vector elements is not legal" assertion.
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; It should at least successfully build.
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define void @autogen_SD3926023935(i8*, i32*, i64*, i32, i64, i8) {
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BB:
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%A4 = alloca i1
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%A3 = alloca float
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%A2 = alloca double
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%A1 = alloca float
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%A = alloca double
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%L = load i8* %0
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store i8 -123, i8* %0
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%E = extractelement <4 x i64> zeroinitializer, i32 1
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%Shuff = shufflevector <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%I = insertelement <2 x i1> zeroinitializer, i1 false, i32 0
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%BC = bitcast i64 181325 to double
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%Sl = select i1 false, <2 x i32> zeroinitializer, <2 x i32> zeroinitializer
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%Cmp = icmp ne <4 x i64> zeroinitializer, zeroinitializer
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%L5 = load i8* %0
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store i8 %L, i8* %0
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%E6 = extractelement <4 x i64> zeroinitializer, i32 3
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%Shuff7 = shufflevector <2 x i16> zeroinitializer, <2 x i16> zeroinitializer, <2 x i32> <i32 2, i32 0>
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%I8 = insertelement <8 x i64> <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1>, i64 498254, i32 4
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%B = shl i32 0, 364464
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%Sl9 = select i1 false, i64 %E, i64 498254
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%Cmp10 = icmp sge i8 -123, %5
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br label %CF80
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CF80: ; preds = %BB
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%L11 = load i8* %0
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store i8 -123, i8* %0
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%E12 = extractelement <2 x i16> zeroinitializer, i32 1
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%Shuff13 = shufflevector <4 x i64> zeroinitializer, <4 x i64> zeroinitializer, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%I14 = insertelement <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, i32 %B, i32 2
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%B15 = sdiv i64 334618, -1
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%PC = bitcast i1* %A4 to i64*
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%Sl16 = select i1 %Cmp10, <4 x i32> zeroinitializer, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
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%Cmp17 = icmp ule <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, %Sl16
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%L18 = load double* %A2
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store i64 498254, i64* %PC
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%E19 = extractelement <4 x i64> zeroinitializer, i32 0
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%Shuff20 = shufflevector <2 x i1> zeroinitializer, <2 x i1> %I, <2 x i32> <i32 3, i32 1>
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%I21 = insertelement <2 x i1> zeroinitializer, i1 false, i32 1
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%B22 = fadd double 0.000000e+00, %BC
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%ZE = zext <2 x i1> %Shuff20 to <2 x i32>
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%Sl23 = select i1 %Cmp10, <2 x i1> %Shuff20, <2 x i1> zeroinitializer
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%Cmp24 = icmp ult <2 x i32> zeroinitializer, zeroinitializer
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%L25 = load i8* %0
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store i8 %L25, i8* %0
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%E26 = extractelement <4 x i8> <i8 -1, i8 -1, i8 -1, i8 -1>, i32 3
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%Shuff27 = shufflevector <4 x i32> %Shuff, <4 x i32> %I14, <4 x i32> <i32 6, i32 0, i32 undef, i32 4>
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%I28 = insertelement <4 x i32> zeroinitializer, i32 %3, i32 0
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%B29 = lshr i8 %E26, -43
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%Tr = trunc i8 %L5 to i1
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br label %CF79
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CF79: ; preds = %CF80
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%Sl30 = select i1 false, i8 %B29, i8 -123
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%Cmp31 = icmp sge <2 x i1> %I, %I
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%L32 = load i64* %PC
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store i8 -123, i8* %0
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%E33 = extractelement <8 x i64> <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1>, i32 2
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%Shuff34 = shufflevector <4 x i64> zeroinitializer, <4 x i64> %Shuff13, <4 x i32> <i32 5, i32 7, i32 1, i32 3>
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%I35 = insertelement <4 x i64> zeroinitializer, i64 498254, i32 3
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%B36 = sub <8 x i64> %I8, <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1>
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%PC37 = bitcast i8* %0 to i1*
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%Sl38 = select i1 %Cmp10, i8 -43, i8 %L5
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%Cmp39 = icmp eq i64 498254, %B15
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br label %CF
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CF: ; preds = %CF, %CF79
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%L40 = load double* %A
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store i1 %Cmp39, i1* %PC37
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%E41 = extractelement <4 x i64> zeroinitializer, i32 3
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%Shuff42 = shufflevector <2 x i32> zeroinitializer, <2 x i32> %ZE, <2 x i32> <i32 2, i32 undef>
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%I43 = insertelement <4 x i32> %Shuff, i32 %3, i32 0
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%B44 = shl i64 %E41, -1
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%Se = sext <2 x i1> %I to <2 x i32>
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%Sl45 = select i1 %Cmp10, i1 false, i1 false
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br i1 %Sl45, label %CF, label %CF77
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CF77: ; preds = %CF77, %CF
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%Cmp46 = fcmp uno double 0.000000e+00, 0.000000e+00
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br i1 %Cmp46, label %CF77, label %CF78
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CF78: ; preds = %CF78, %CF83, %CF82, %CF77
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%L47 = load i64* %PC
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store i8 -123, i8* %0
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%E48 = extractelement <4 x i64> zeroinitializer, i32 3
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%Shuff49 = shufflevector <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> zeroinitializer, <4 x i32> <i32 2, i32 4, i32 6, i32 undef>
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%I50 = insertelement <2 x i1> zeroinitializer, i1 %Cmp10, i32 0
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%B51 = sdiv i64 %E19, 463132
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%Tr52 = trunc i64 %E48 to i32
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%Sl53 = select i1 %Tr, i1 %Cmp46, i1 %Cmp10
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br i1 %Sl53, label %CF78, label %CF83
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CF83: ; preds = %CF78
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%Cmp54 = fcmp uge double %L40, %L40
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br i1 %Cmp54, label %CF78, label %CF82
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CF82: ; preds = %CF83
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%L55 = load i64* %PC
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store i64 %L32, i64* %PC
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%E56 = extractelement <2 x i16> %Shuff7, i32 1
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%Shuff57 = shufflevector <4 x i64> zeroinitializer, <4 x i64> zeroinitializer, <4 x i32> <i32 2, i32 4, i32 6, i32 0>
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%I58 = insertelement <2 x i32> %Sl, i32 %Tr52, i32 0
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%B59 = or i32 %B, %3
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%FC = sitofp i64 498254 to double
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%Sl60 = select i1 false, i64 %E6, i64 -1
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%Cmp61 = icmp sgt <4 x i32> %Shuff27, %I43
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%L62 = load i64* %PC
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store i64 %Sl9, i64* %PC
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%E63 = extractelement <2 x i32> %ZE, i32 0
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%Shuff64 = shufflevector <4 x i64> zeroinitializer, <4 x i64> %Shuff13, <4 x i32> <i32 1, i32 3, i32 undef, i32 7>
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%I65 = insertelement <4 x i32> %Shuff, i32 %3, i32 3
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%B66 = sub i64 %L47, 53612
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%Tr67 = trunc i64 %4 to i32
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%Sl68 = select i1 %Cmp39, i1 %Cmp39, i1 false
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br i1 %Sl68, label %CF78, label %CF81
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CF81: ; preds = %CF82
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%Cmp69 = icmp ne <8 x i64> <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1>, %B36
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%L70 = load i8* %0
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store i64 %L55, i64* %PC
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%E71 = extractelement <4 x i32> %Shuff49, i32 1
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%Shuff72 = shufflevector <4 x i64> zeroinitializer, <4 x i64> %Shuff34, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%I73 = insertelement <4 x i64> %Shuff64, i64 %E, i32 2
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%B74 = lshr <8 x i64> <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1>, %B36
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%Sl75 = select i1 %Sl68, i64 %B51, i64 %L55
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%Cmp76 = icmp sgt <8 x i64> %B74, %B36
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store i1 %Cmp39, i1* %PC37
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store i64 %E41, i64* %PC
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store i64 %L32, i64* %PC
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store i64 %Sl75, i64* %2
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store i64 %L32, i64* %PC
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ret void
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}
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