forked from OSchip/llvm-project
[VE] Update ISel patterns for select instruction
Add an ISel pattern for fp128 select instruction and optimize generated code for other types' select. instructions. Add a regression test also. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D89509
This commit is contained in:
Kazushi (Jam) Marukawa
parent
e7c90418fc
commit
af8b444de3
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@ -1773,6 +1773,7 @@ let Uses = [SX11], hasSideEffects = 1 in
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def GETSTACKTOP : Pseudo<(outs I64:$dst), (ins),
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"# GET STACK TOP",
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[(set iPTR:$dst, (GetStackTop))]>;
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// SETCC pattern matches
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//
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// CMP %tmp, lhs, rhs ; compare lhs and rhs
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@ -1860,6 +1861,41 @@ def : Pat<(i64 (selectcc i64:$LHS, i64:$RHS, i64:$LHS, i64:$RHS, SETLE)),
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def : Pat<(i32 (selectcc i32:$LHS, i32:$RHS, i32:$LHS, i32:$RHS, SETLE)),
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(MINSWSXrr $LHS, $RHS)>;
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// Helper classes to construct cmov patterns for the ease.
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//
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// Hiding INSERT_SUBREG/EXTRACT_SUBREG patterns.
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class cmovrr<Instruction INSN> :
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OutPatFrag<(ops node:$cond, node:$comp, node:$t, node:$f),
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(INSN $cond, $comp, $t, $f)>;
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class cmovrm<Instruction INSN, SDNodeXForm MOP = MIMM> :
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OutPatFrag<(ops node:$cond, node:$comp, node:$t, node:$f),
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(INSN $cond, $comp, (MOP $t), $f)>;
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class cmov32rr<Instruction INSN, SubRegIndex sub_oty> :
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OutPatFrag<(ops node:$cond, node:$comp, node:$t, node:$f),
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(EXTRACT_SUBREG
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(INSN $cond, $comp,
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(INSERT_SUBREG (i64 (IMPLICIT_DEF)), $t, sub_oty),
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(INSERT_SUBREG (i64 (IMPLICIT_DEF)), $f, sub_oty)),
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sub_oty)>;
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class cmov32rm<Instruction INSN, SubRegIndex sub_oty, SDNodeXForm MOP = MIMM> :
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OutPatFrag<(ops node:$cond, node:$comp, node:$t, node:$f),
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(EXTRACT_SUBREG
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(INSN $cond, $comp,
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(MOP $t),
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(INSERT_SUBREG (i64 (IMPLICIT_DEF)), $f, sub_oty)),
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sub_oty)>;
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class cmov128rr<Instruction INSN> :
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OutPatFrag<(ops node:$cond, node:$comp, node:$t, node:$f),
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(INSERT_SUBREG
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(INSERT_SUBREG (f128 (IMPLICIT_DEF)),
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(INSN $cond, $comp,
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(EXTRACT_SUBREG $t, sub_odd),
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(EXTRACT_SUBREG $f, sub_odd)), sub_odd),
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(INSN $cond, $comp,
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(EXTRACT_SUBREG $t, sub_even),
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(EXTRACT_SUBREG $f, sub_even)), sub_even)>;
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// Generic SELECTCC pattern matches
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//
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// CMP %tmp, %l, %r ; compare %l and %r
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@ -1987,25 +2023,36 @@ def : Pat<(f32 (selectcc f64:$l, f64:$r, f32:$t, f32:$f, cond:$cond)),
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//
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// CMOV.w.ne %res, %tval, %tmp ; set tval if %tmp is true
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def : Pat<(i64 (select i32:$pred, i64:$t, i64:$f)),
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(CMOVWrr CC_INE, $pred, $t, $f)>;
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def : Pat<(i32 (select i32:$pred, i32:$t, i32:$f)),
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(EXTRACT_SUBREG
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(CMOVWrr CC_INE, $pred,
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(INSERT_SUBREG (i64 (IMPLICIT_DEF)), $t, sub_i32),
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(INSERT_SUBREG (i64 (IMPLICIT_DEF)), $f, sub_i32)),
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sub_i32)>;
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(cmov32rr<CMOVWrr, sub_i32> CC_INE, $pred, $t, $f)>;
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def : Pat<(i32 (select i32:$pred, (i32 mimm:$t), i32:$f)),
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(cmov32rm<CMOVWrm, sub_i32> CC_INE, $pred, $t, $f)>;
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def : Pat<(i32 (select i32:$pred, i32:$t, (i32 mimm:$f))),
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(cmov32rm<CMOVWrm, sub_i32> CC_IEQ, $pred, $f, $t)>;
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def : Pat<(f64 (select i32:$pred, f64:$t, f64:$f)),
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(CMOVWrr CC_INE, $pred, $t, $f)>;
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def : Pat<(i64 (select i32:$pred, i64:$t, i64:$f)),
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(cmovrr<CMOVWrr> CC_INE, $pred, $t, $f)>;
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def : Pat<(i64 (select i32:$pred, (i64 mimm:$t), i64:$f)),
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(cmovrm<CMOVWrm, MIMM> CC_INE, $pred, $t, $f)>;
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def : Pat<(i64 (select i32:$pred, i64:$t, (i64 mimm:$f))),
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(cmovrm<CMOVWrm, MIMM> CC_IEQ, $pred, $f, $t)>;
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def : Pat<(f32 (select i32:$pred, f32:$t, f32:$f)),
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(EXTRACT_SUBREG
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(CMOVWrr CC_INE, $pred,
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(INSERT_SUBREG (i64 (IMPLICIT_DEF)), $t, sub_f32),
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(INSERT_SUBREG (i64 (IMPLICIT_DEF)), $f, sub_f32)),
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sub_f32)>;
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(cmov32rr<CMOVWrr, sub_f32> CC_INE, $pred, $t, $f)>;
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def : Pat<(f32 (select i32:$pred, (f32 mimmfp:$t), f32:$f)),
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(cmov32rm<CMOVWrm, sub_f32, MIMMFP> CC_INE, $pred, $t, $f)>;
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def : Pat<(f32 (select i32:$pred, f32:$t, (f32 mimmfp:$f))),
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(cmov32rm<CMOVWrm, sub_f32, MIMMFP> CC_IEQ, $pred, $f, $t)>;
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def : Pat<(f64 (select i32:$pred, f64:$t, f64:$f)),
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(cmovrr<CMOVWrr> CC_INE, $pred, $t, $f)>;
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def : Pat<(f64 (select i32:$pred, (f64 mimmfp:$t), f64:$f)),
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(cmovrm<CMOVWrm, MIMMFP> CC_INE, $pred, $t, $f)>;
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def : Pat<(f64 (select i32:$pred, f64:$t, (f64 mimmfp:$f))),
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(cmovrm<CMOVWrm, MIMMFP> CC_IEQ, $pred, $f, $t)>;
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def : Pat<(f128 (select i32:$pred, f128:$t, f128:$f)),
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(cmov128rr<CMOVWrr> CC_INE, $pred, $t, $f)>;
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// bitconvert
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def : Pat<(f64 (bitconvert i64:$src)), (COPY_TO_REGCLASS $src, I64)>;
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@ -15,9 +15,8 @@ define void @func() {
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; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: lea.sl %s0, src@gotoff_hi(, %s0)
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; CHECK-NEXT: ld1b.zx %s0, (%s0, %s15)
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; CHECK-NEXT: or %s1, 0, (0)1
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; CHECK-NEXT: lea %s2, 100
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; CHECK-NEXT: cmov.w.ne %s1, %s2, %s0
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; CHECK-NEXT: lea %s1, 100
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; CHECK-NEXT: cmov.w.eq %s1, (0)1, %s0
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; CHECK-NEXT: lea %s0, dst@gotoff_lo
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; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: lea.sl %s0, dst@gotoff_hi(, %s0)
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@ -1,29 +1,123 @@
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; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
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; RUN: llc < %s -mtriple=ve | FileCheck %s
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define double @selectf64(i1 zeroext, double, double) {
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; CHECK-LABEL: selectf64:
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;;; Test ‘select’ instruction
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;;;
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;;; Syntax:
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;;; <result> = select [fast-math flags] selty <cond>, <ty> <val1>, <ty> <val2>
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;;; ; yields ty
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;;;
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;;; selty is either i1 or {<N x i1>}
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;;;
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;;; Overview:
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;;; The ‘select’ instruction is used to choose one value based on a condition,
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;;; without IR-level branching.
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;;;
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;;; Arguments:
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;;; The ‘select’ instruction requires an ‘i1’ value or a vector of ‘i1’ values
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;;; indicating the condition, and two values of the same first class type.
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;;;
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;;; The optional fast-math flags marker indicates that the select has one or
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;;; more fast-math flags. These are optimization hints to enable otherwise
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;;; unsafe floating-point optimizations. Fast-math flags are only valid for
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;;; selects that return a floating-point scalar or vector type, or an array
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;;; (nested to any depth) of floating-point scalar or vector types.
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;;;
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;;; Semantics:
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;;; If the condition is an i1 and it evaluates to 1, the instruction returns
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;;; the first value argument; otherwise, it returns the second value argument.
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;;;
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;;; If the condition is a vector of i1, then the value arguments must be
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;;; vectors of the same size, and the selection is done element by element.
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;;;
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;;; If the condition is an i1 and the value arguments are vectors of the same
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;;; size, then an entire vector is selected.
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;;;
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;;; Example:
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;;; %X = select i1 true, i8 17, i8 42 ; yields i8:17
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;;;
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;;; Note:
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;;; We test only i1/i8/u8/i16/u16/i32/u32/i64/u64/i128/u128/float/double/fp128
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; Function Attrs: norecurse nounwind readnone
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define zeroext i1 @select_i1_var(i1 zeroext %0, i1 zeroext %1, i1 zeroext %2) {
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; CHECK-LABEL: select_i1_var:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
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; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0
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; CHECK-NEXT: or %s0, 0, %s2
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; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1
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; CHECK-NEXT: or %s11, 0, %s9
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%4 = select i1 %0, double %1, double %2
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ret double %4
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%4 = select i1 %0, i1 %1, i1 %2
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ret i1 %4
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}
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define float @selectf32(i1 zeroext, float, float) {
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; CHECK-LABEL: selectf32:
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; Function Attrs: norecurse nounwind readnone
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define signext i8 @select_i8_var(i1 zeroext %0, i8 signext %1, i8 signext %2) {
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; CHECK-LABEL: select_i8_var:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
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; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0
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; CHECK-NEXT: or %s0, 0, %s2
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; CHECK-NEXT: adds.w.sx %s0, %s2, (0)1
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; CHECK-NEXT: or %s11, 0, %s9
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%4 = select i1 %0, float %1, float %2
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ret float %4
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%4 = select i1 %0, i8 %1, i8 %2
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ret i8 %4
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}
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define i64 @selecti64(i1 zeroext, i64, i64) {
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; CHECK-LABEL: selecti64:
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; Function Attrs: norecurse nounwind readnone
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define zeroext i8 @select_u8_var(i1 zeroext %0, i8 zeroext %1, i8 zeroext %2) {
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; CHECK-LABEL: select_u8_var:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0
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; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1
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; CHECK-NEXT: or %s11, 0, %s9
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%4 = select i1 %0, i8 %1, i8 %2
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ret i8 %4
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}
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; Function Attrs: norecurse nounwind readnone
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define signext i16 @select_i16_var(i1 zeroext %0, i16 signext %1, i16 signext %2) {
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; CHECK-LABEL: select_i16_var:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0
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; CHECK-NEXT: adds.w.sx %s0, %s2, (0)1
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; CHECK-NEXT: or %s11, 0, %s9
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%4 = select i1 %0, i16 %1, i16 %2
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ret i16 %4
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}
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; Function Attrs: norecurse nounwind readnone
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define zeroext i16 @select_u16_var(i1 zeroext %0, i16 zeroext %1, i16 zeroext %2) {
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; CHECK-LABEL: select_u16_var:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0
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; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1
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; CHECK-NEXT: or %s11, 0, %s9
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%4 = select i1 %0, i16 %1, i16 %2
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ret i16 %4
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}
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; Function Attrs: norecurse nounwind readnone
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define signext i32 @select_i32_var(i1 zeroext %0, i32 signext %1, i32 signext %2) {
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; CHECK-LABEL: select_i32_var:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0
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; CHECK-NEXT: adds.w.sx %s0, %s2, (0)1
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; CHECK-NEXT: or %s11, 0, %s9
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%4 = select i1 %0, i32 %1, i32 %2
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ret i32 %4
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}
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; Function Attrs: norecurse nounwind readnone
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define zeroext i32 @select_u32_var(i1 zeroext %0, i32 zeroext %1, i32 zeroext %2) {
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; CHECK-LABEL: select_u32_var:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0
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; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1
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; CHECK-NEXT: or %s11, 0, %s9
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%4 = select i1 %0, i32 %1, i32 %2
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ret i32 %4
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}
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; Function Attrs: norecurse nounwind readnone
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define i64 @select_i64_var(i1 zeroext %0, i64 %1, i64 %2) {
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; CHECK-LABEL: select_i64_var:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
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; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0
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@ -33,22 +127,424 @@ define i64 @selecti64(i1 zeroext, i64, i64) {
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ret i64 %4
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}
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define i32 @selecti32(i1 zeroext, i32, i32) {
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; CHECK-LABEL: selecti32:
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; Function Attrs: norecurse nounwind readnone
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define i64 @select_u64_var(i1 zeroext %0, i64 %1, i64 %2) {
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; CHECK-LABEL: select_u64_var:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
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; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0
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; CHECK-NEXT: or %s0, 0, %s2
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; CHECK-NEXT: or %s11, 0, %s9
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%4 = select i1 %0, i32 %1, i32 %2
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ret i32 %4
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%4 = select i1 %0, i64 %1, i64 %2
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ret i64 %4
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}
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define zeroext i1 @selecti1(i1 zeroext, i1 zeroext, i1 zeroext) {
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; CHECK-LABEL: selecti1:
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; Function Attrs: norecurse nounwind readnone
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define i128 @select_i128_var(i1 zeroext %0, i128 %1, i128 %2) {
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; CHECK-LABEL: select_i128_var:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0
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; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1
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; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
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; CHECK-NEXT: cmov.w.ne %s3, %s1, %s0
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; CHECK-NEXT: cmov.w.ne %s4, %s2, %s0
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; CHECK-NEXT: or %s0, 0, %s3
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; CHECK-NEXT: or %s1, 0, %s4
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; CHECK-NEXT: or %s11, 0, %s9
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%4 = select i1 %0, i1 %1, i1 %2
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%4 = select i1 %0, i128 %1, i128 %2
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ret i128 %4
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}
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; Function Attrs: norecurse nounwind readnone
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define i128 @select_u128_var(i1 zeroext %0, i128 %1, i128 %2) {
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; CHECK-LABEL: select_u128_var:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
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; CHECK-NEXT: cmov.w.ne %s3, %s1, %s0
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; CHECK-NEXT: cmov.w.ne %s4, %s2, %s0
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; CHECK-NEXT: or %s0, 0, %s3
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; CHECK-NEXT: or %s1, 0, %s4
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; CHECK-NEXT: or %s11, 0, %s9
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%4 = select i1 %0, i128 %1, i128 %2
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ret i128 %4
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}
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; Function Attrs: norecurse nounwind readnone
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define float @select_float_var(i1 zeroext %0, float %1, float %2) {
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; CHECK-LABEL: select_float_var:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
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; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0
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; CHECK-NEXT: or %s0, 0, %s2
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; CHECK-NEXT: or %s11, 0, %s9
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%4 = select fast i1 %0, float %1, float %2
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ret float %4
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}
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; Function Attrs: norecurse nounwind readnone
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define double @select_double_var(i1 zeroext %0, double %1, double %2) {
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; CHECK-LABEL: select_double_var:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
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; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0
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; CHECK-NEXT: or %s0, 0, %s2
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; CHECK-NEXT: or %s11, 0, %s9
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%4 = select fast i1 %0, double %1, double %2
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ret double %4
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}
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; Function Attrs: norecurse nounwind readnone
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define fp128 @select_quad_var(i1 zeroext %0, fp128 %1, fp128 %2) {
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; CHECK-LABEL: select_quad_var:
|
||||
; CHECK: .LBB{{[0-9]+}}_2:
|
||||
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
|
||||
; CHECK-NEXT: cmov.w.ne %s4, %s2, %s0
|
||||
; CHECK-NEXT: cmov.w.ne %s5, %s3, %s0
|
||||
; CHECK-NEXT: or %s0, 0, %s4
|
||||
; CHECK-NEXT: or %s1, 0, %s5
|
||||
; CHECK-NEXT: or %s11, 0, %s9
|
||||
%4 = select fast i1 %0, fp128 %1, fp128 %2
|
||||
ret fp128 %4
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind readnone
|
||||
define zeroext i1 @select_i1_mimm(i1 zeroext %0, i1 zeroext %1) {
|
||||
; CHECK-LABEL: select_i1_mimm:
|
||||
; CHECK: .LBB{{[0-9]+}}_2:
|
||||
; CHECK-NEXT: or %s0, %s0, %s1
|
||||
; CHECK-NEXT: or %s11, 0, %s9
|
||||
%3 = or i1 %0, %1
|
||||
ret i1 %3
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind readnone
|
||||
define signext i8 @select_i8_mimm(i1 zeroext %0, i8 signext %1) {
|
||||
; CHECK-LABEL: select_i8_mimm:
|
||||
; CHECK: .LBB{{[0-9]+}}_2:
|
||||
; CHECK-NEXT: cmov.w.ne %s1, (57)1, %s0
|
||||
; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1
|
||||
; CHECK-NEXT: or %s11, 0, %s9
|
||||
%3 = select i1 %0, i8 -128, i8 %1
|
||||
ret i8 %3
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind readnone
|
||||
define zeroext i8 @select_u8_mimm(i1 zeroext %0, i8 zeroext %1) {
|
||||
; CHECK-LABEL: select_u8_mimm:
|
||||
; CHECK: .LBB{{[0-9]+}}_2:
|
||||
; CHECK-NEXT: cmov.w.ne %s1, (57)0, %s0
|
||||
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
|
||||
; CHECK-NEXT: or %s11, 0, %s9
|
||||
%3 = select i1 %0, i8 127, i8 %1
|
||||
ret i8 %3
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind readnone
|
||||
define signext i16 @select_i16_mimm(i1 zeroext %0, i16 signext %1) {
|
||||
; CHECK-LABEL: select_i16_mimm:
|
||||
; CHECK: .LBB{{[0-9]+}}_2:
|
||||
; CHECK-NEXT: cmov.w.ne %s1, (49)1, %s0
|
||||
; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1
|
||||
; CHECK-NEXT: or %s11, 0, %s9
|
||||
%3 = select i1 %0, i16 -32768, i16 %1
|
||||
ret i16 %3
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind readnone
|
||||
define zeroext i16 @select_u16_mimm(i1 zeroext %0, i16 zeroext %1) {
|
||||
; CHECK-LABEL: select_u16_mimm:
|
||||
; CHECK: .LBB{{[0-9]+}}_2:
|
||||
; CHECK-NEXT: cmov.w.ne %s1, (49)0, %s0
|
||||
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
|
||||
; CHECK-NEXT: or %s11, 0, %s9
|
||||
%3 = select i1 %0, i16 32767, i16 %1
|
||||
ret i16 %3
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind readnone
|
||||
define signext i32 @select_i32_mimm(i1 zeroext %0, i32 signext %1) {
|
||||
; CHECK-LABEL: select_i32_mimm:
|
||||
; CHECK: .LBB{{[0-9]+}}_2:
|
||||
; CHECK-NEXT: cmov.w.ne %s1, (48)0, %s0
|
||||
; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1
|
||||
; CHECK-NEXT: or %s11, 0, %s9
|
||||
%3 = select i1 %0, i32 65535, i32 %1
|
||||
ret i32 %3
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind readnone
|
||||
define zeroext i32 @select_u32_mimm(i1 zeroext %0, i32 zeroext %1) {
|
||||
; CHECK-LABEL: select_u32_mimm:
|
||||
; CHECK: .LBB{{[0-9]+}}_2:
|
||||
; CHECK-NEXT: cmov.w.ne %s1, (48)0, %s0
|
||||
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
|
||||
; CHECK-NEXT: or %s11, 0, %s9
|
||||
%3 = select i1 %0, i32 65535, i32 %1
|
||||
ret i32 %3
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind readnone
|
||||
define i64 @select_i64_mimm(i1 zeroext %0, i64 %1) {
|
||||
; CHECK-LABEL: select_i64_mimm:
|
||||
; CHECK: .LBB{{[0-9]+}}_2:
|
||||
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
|
||||
; CHECK-NEXT: cmov.w.ne %s1, (48)0, %s0
|
||||
; CHECK-NEXT: or %s0, 0, %s1
|
||||
; CHECK-NEXT: or %s11, 0, %s9
|
||||
%3 = select i1 %0, i64 65535, i64 %1
|
||||
ret i64 %3
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind readnone
|
||||
define i64 @select_u64_mimm(i1 zeroext %0, i64 %1) {
|
||||
; CHECK-LABEL: select_u64_mimm:
|
||||
; CHECK: .LBB{{[0-9]+}}_2:
|
||||
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
|
||||
; CHECK-NEXT: cmov.w.ne %s1, (48)0, %s0
|
||||
; CHECK-NEXT: or %s0, 0, %s1
|
||||
; CHECK-NEXT: or %s11, 0, %s9
|
||||
%3 = select i1 %0, i64 65535, i64 %1
|
||||
ret i64 %3
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind readnone
|
||||
define i128 @select_i128_mimm(i1 zeroext %0, i128 %1) {
|
||||
; CHECK-LABEL: select_i128_mimm:
|
||||
; CHECK: .LBB{{[0-9]+}}_2:
|
||||
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
|
||||
; CHECK-NEXT: cmov.w.ne %s1, (48)0, %s0
|
||||
; CHECK-NEXT: cmov.w.ne %s2, (0)1, %s0
|
||||
; CHECK-NEXT: or %s0, 0, %s1
|
||||
; CHECK-NEXT: or %s1, 0, %s2
|
||||
; CHECK-NEXT: or %s11, 0, %s9
|
||||
%3 = select i1 %0, i128 65535, i128 %1
|
||||
ret i128 %3
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind readnone
|
||||
define i128 @select_u128_mimm(i1 zeroext %0, i128 %1) {
|
||||
; CHECK-LABEL: select_u128_mimm:
|
||||
; CHECK: .LBB{{[0-9]+}}_2:
|
||||
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
|
||||
; CHECK-NEXT: cmov.w.ne %s1, (48)0, %s0
|
||||
; CHECK-NEXT: cmov.w.ne %s2, (0)1, %s0
|
||||
; CHECK-NEXT: or %s0, 0, %s1
|
||||
; CHECK-NEXT: or %s1, 0, %s2
|
||||
; CHECK-NEXT: or %s11, 0, %s9
|
||||
%3 = select i1 %0, i128 65535, i128 %1
|
||||
ret i128 %3
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind readnone
|
||||
define float @select_float_mimm(i1 zeroext %0, float %1) {
|
||||
; CHECK-LABEL: select_float_mimm:
|
||||
; CHECK: .LBB{{[0-9]+}}_2:
|
||||
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
|
||||
; CHECK-NEXT: cmov.w.ne %s1, (2)1, %s0
|
||||
; CHECK-NEXT: or %s0, 0, %s1
|
||||
; CHECK-NEXT: or %s11, 0, %s9
|
||||
%3 = select i1 %0, float -2.000000e+00, float %1
|
||||
ret float %3
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind readnone
|
||||
define double @select_double_mimm(i1 zeroext %0, double %1) {
|
||||
; CHECK-LABEL: select_double_mimm:
|
||||
; CHECK: .LBB{{[0-9]+}}_2:
|
||||
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
|
||||
; CHECK-NEXT: cmov.w.ne %s1, (2)1, %s0
|
||||
; CHECK-NEXT: or %s0, 0, %s1
|
||||
; CHECK-NEXT: or %s11, 0, %s9
|
||||
%3 = select fast i1 %0, double -2.000000e+00, double %1
|
||||
ret double %3
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind readnone
|
||||
define fp128 @select_quad_mimm(i1 zeroext %0, fp128 %1) {
|
||||
; CHECK-LABEL: select_quad_mimm:
|
||||
; CHECK: .LBB{{[0-9]+}}_2:
|
||||
; CHECK-NEXT: lea %s1, .LCPI{{[0-9]+}}_0@lo
|
||||
; CHECK-NEXT: and %s1, %s1, (32)0
|
||||
; CHECK-NEXT: lea.sl %s1, .LCPI{{[0-9]+}}_0@hi(, %s1)
|
||||
; CHECK-NEXT: ld %s4, 8(, %s1)
|
||||
; CHECK-NEXT: ld %s5, (, %s1)
|
||||
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
|
||||
; CHECK-NEXT: cmov.w.ne %s2, %s4, %s0
|
||||
; CHECK-NEXT: cmov.w.ne %s3, %s5, %s0
|
||||
; CHECK-NEXT: or %s0, 0, %s2
|
||||
; CHECK-NEXT: or %s1, 0, %s3
|
||||
; CHECK-NEXT: or %s11, 0, %s9
|
||||
%3 = select fast i1 %0, fp128 0xL0000000000000000C000000000000000, fp128 %1
|
||||
ret fp128 %3
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind readnone
|
||||
define zeroext i1 @select_mimm_i1(i1 zeroext %0, i1 zeroext %1) {
|
||||
; CHECK-LABEL: select_mimm_i1:
|
||||
; CHECK: .LBB{{[0-9]+}}_2:
|
||||
; CHECK-NEXT: xor %s0, 1, %s0
|
||||
; CHECK-NEXT: or %s0, %s0, %s1
|
||||
; CHECK-NEXT: or %s11, 0, %s9
|
||||
%3 = xor i1 %0, true
|
||||
%4 = or i1 %3, %1
|
||||
ret i1 %4
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind readnone
|
||||
define signext i8 @select_mimm_i8(i1 zeroext %0, i8 signext %1) {
|
||||
; CHECK-LABEL: select_mimm_i8:
|
||||
; CHECK: .LBB{{[0-9]+}}_2:
|
||||
; CHECK-NEXT: cmov.w.eq %s1, (57)1, %s0
|
||||
; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1
|
||||
; CHECK-NEXT: or %s11, 0, %s9
|
||||
%3 = select i1 %0, i8 %1, i8 -128
|
||||
ret i8 %3
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind readnone
|
||||
define zeroext i8 @select_mimm_u8(i1 zeroext %0, i8 zeroext %1) {
|
||||
; CHECK-LABEL: select_mimm_u8:
|
||||
; CHECK: .LBB{{[0-9]+}}_2:
|
||||
; CHECK-NEXT: cmov.w.eq %s1, (57)0, %s0
|
||||
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
|
||||
; CHECK-NEXT: or %s11, 0, %s9
|
||||
%3 = select i1 %0, i8 %1, i8 127
|
||||
ret i8 %3
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind readnone
|
||||
define signext i16 @select_mimm_i16(i1 zeroext %0, i16 signext %1) {
|
||||
; CHECK-LABEL: select_mimm_i16:
|
||||
; CHECK: .LBB{{[0-9]+}}_2:
|
||||
; CHECK-NEXT: cmov.w.eq %s1, (49)1, %s0
|
||||
; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1
|
||||
; CHECK-NEXT: or %s11, 0, %s9
|
||||
%3 = select i1 %0, i16 %1, i16 -32768
|
||||
ret i16 %3
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind readnone
|
||||
define zeroext i16 @select_mimm_u16(i1 zeroext %0, i16 zeroext %1) {
|
||||
; CHECK-LABEL: select_mimm_u16:
|
||||
; CHECK: .LBB{{[0-9]+}}_2:
|
||||
; CHECK-NEXT: cmov.w.eq %s1, (49)0, %s0
|
||||
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
|
||||
; CHECK-NEXT: or %s11, 0, %s9
|
||||
%3 = select i1 %0, i16 %1, i16 32767
|
||||
ret i16 %3
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind readnone
|
||||
define signext i32 @select_mimm_i32(i1 zeroext %0, i32 signext %1) {
|
||||
; CHECK-LABEL: select_mimm_i32:
|
||||
; CHECK: .LBB{{[0-9]+}}_2:
|
||||
; CHECK-NEXT: cmov.w.eq %s1, (48)0, %s0
|
||||
; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1
|
||||
; CHECK-NEXT: or %s11, 0, %s9
|
||||
%3 = select i1 %0, i32 %1, i32 65535
|
||||
ret i32 %3
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind readnone
|
||||
define zeroext i32 @select_mimm_u32(i1 zeroext %0, i32 zeroext %1) {
|
||||
; CHECK-LABEL: select_mimm_u32:
|
||||
; CHECK: .LBB{{[0-9]+}}_2:
|
||||
; CHECK-NEXT: cmov.w.eq %s1, (48)0, %s0
|
||||
; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
|
||||
; CHECK-NEXT: or %s11, 0, %s9
|
||||
%3 = select i1 %0, i32 %1, i32 65535
|
||||
ret i32 %3
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind readnone
|
||||
define i64 @select_mimm_i64(i1 zeroext %0, i64 %1) {
|
||||
; CHECK-LABEL: select_mimm_i64:
|
||||
; CHECK: .LBB{{[0-9]+}}_2:
|
||||
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
|
||||
; CHECK-NEXT: cmov.w.eq %s1, (48)0, %s0
|
||||
; CHECK-NEXT: or %s0, 0, %s1
|
||||
; CHECK-NEXT: or %s11, 0, %s9
|
||||
%3 = select i1 %0, i64 %1, i64 65535
|
||||
ret i64 %3
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind readnone
|
||||
define i64 @select_mimm_u64(i1 zeroext %0, i64 %1) {
|
||||
; CHECK-LABEL: select_mimm_u64:
|
||||
; CHECK: .LBB{{[0-9]+}}_2:
|
||||
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
|
||||
; CHECK-NEXT: cmov.w.eq %s1, (48)0, %s0
|
||||
; CHECK-NEXT: or %s0, 0, %s1
|
||||
; CHECK-NEXT: or %s11, 0, %s9
|
||||
%3 = select i1 %0, i64 %1, i64 65535
|
||||
ret i64 %3
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind readnone
|
||||
define i128 @select_mimm_i128(i1 zeroext %0, i128 %1) {
|
||||
; CHECK-LABEL: select_mimm_i128:
|
||||
; CHECK: .LBB{{[0-9]+}}_2:
|
||||
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
|
||||
; CHECK-NEXT: cmov.w.eq %s1, (48)0, %s0
|
||||
; CHECK-NEXT: cmov.w.eq %s2, (0)1, %s0
|
||||
; CHECK-NEXT: or %s0, 0, %s1
|
||||
; CHECK-NEXT: or %s1, 0, %s2
|
||||
; CHECK-NEXT: or %s11, 0, %s9
|
||||
%3 = select i1 %0, i128 %1, i128 65535
|
||||
ret i128 %3
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind readnone
|
||||
define i128 @select_mimm_u128(i1 zeroext %0, i128 %1) {
|
||||
; CHECK-LABEL: select_mimm_u128:
|
||||
; CHECK: .LBB{{[0-9]+}}_2:
|
||||
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
|
||||
; CHECK-NEXT: cmov.w.eq %s1, (48)0, %s0
|
||||
; CHECK-NEXT: cmov.w.eq %s2, (0)1, %s0
|
||||
; CHECK-NEXT: or %s0, 0, %s1
|
||||
; CHECK-NEXT: or %s1, 0, %s2
|
||||
; CHECK-NEXT: or %s11, 0, %s9
|
||||
%3 = select i1 %0, i128 %1, i128 65535
|
||||
ret i128 %3
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind readnone
|
||||
define float @select_mimm_float(i1 zeroext %0, float %1) {
|
||||
; CHECK-LABEL: select_mimm_float:
|
||||
; CHECK: .LBB{{[0-9]+}}_2:
|
||||
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
|
||||
; CHECK-NEXT: cmov.w.eq %s1, (2)1, %s0
|
||||
; CHECK-NEXT: or %s0, 0, %s1
|
||||
; CHECK-NEXT: or %s11, 0, %s9
|
||||
%3 = select i1 %0, float %1, float -2.000000e+00
|
||||
ret float %3
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind readnone
|
||||
define double @select_mimm_double(i1 zeroext %0, double %1) {
|
||||
; CHECK-LABEL: select_mimm_double:
|
||||
; CHECK: .LBB{{[0-9]+}}_2:
|
||||
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
|
||||
; CHECK-NEXT: cmov.w.eq %s1, (2)1, %s0
|
||||
; CHECK-NEXT: or %s0, 0, %s1
|
||||
; CHECK-NEXT: or %s11, 0, %s9
|
||||
%3 = select fast i1 %0, double %1, double -2.000000e+00
|
||||
ret double %3
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind readnone
|
||||
define fp128 @select_mimm_quad(i1 zeroext %0, fp128 %1) {
|
||||
; CHECK-LABEL: select_mimm_quad:
|
||||
; CHECK: .LBB{{[0-9]+}}_2:
|
||||
; CHECK-NEXT: lea %s1, .LCPI{{[0-9]+}}_0@lo
|
||||
; CHECK-NEXT: and %s1, %s1, (32)0
|
||||
; CHECK-NEXT: lea.sl %s1, .LCPI{{[0-9]+}}_0@hi(, %s1)
|
||||
; CHECK-NEXT: ld %s4, 8(, %s1)
|
||||
; CHECK-NEXT: ld %s5, (, %s1)
|
||||
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
|
||||
; CHECK-NEXT: cmov.w.ne %s4, %s2, %s0
|
||||
; CHECK-NEXT: cmov.w.ne %s5, %s3, %s0
|
||||
; CHECK-NEXT: or %s0, 0, %s4
|
||||
; CHECK-NEXT: or %s1, 0, %s5
|
||||
; CHECK-NEXT: or %s11, 0, %s9
|
||||
%3 = select fast i1 %0, fp128 %1, fp128 0xL0000000000000000C000000000000000
|
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ret fp128 %3
|
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}
|
||||
|
|
|
|||
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Reference in New Issue