forked from OSchip/llvm-project
make Affine parallel and yield ops MemRefsNormalizable
Affine parallel ops may contain and yield results from MemRefsNormalizable ops in the loop body. Thus, both affine.parallel and affine.yield should have the MemRefsNormalizable trait. Reviewed By: bondhugula Differential Revision: https://reviews.llvm.org/D96821
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@ -592,7 +592,7 @@ def AffineMaxOp : AffineMinMaxOpBase<"max", [NoSideEffect]> {
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def AffineParallelOp : Affine_Op<"parallel",
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[ImplicitAffineTerminator, RecursiveSideEffects,
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DeclareOpInterfaceMethods<LoopLikeOpInterface>]> {
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DeclareOpInterfaceMethods<LoopLikeOpInterface>, MemRefsNormalizable]> {
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let summary = "multi-index parallel band operation";
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let description = [{
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The "affine.parallel" operation represents a hyper-rectangular affine
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@ -842,7 +842,8 @@ def AffineStoreOp : AffineStoreOpBase<"store"> {
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let hasFolder = 1;
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}
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def AffineYieldOp : Affine_Op<"yield", [NoSideEffect, Terminator, ReturnLike]> {
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def AffineYieldOp : Affine_Op<"yield", [NoSideEffect, Terminator, ReturnLike,
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MemRefsNormalizable]> {
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let summary = "Yield values to parent operation";
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let description = [{
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"affine.yield" yields zero or more SSA values from an affine op region and
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@ -512,6 +512,10 @@ Operation *NormalizeMemRefs::createOpResultsNormalized(FuncOp funcOp,
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// affine map, `oldOp` is returned without modification.
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if (resultTypeNormalized) {
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OpBuilder bb(oldOp);
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for (auto &oldRegion : oldOp->getRegions()) {
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Region *newRegion = result.addRegion();
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newRegion->takeBody(oldRegion);
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}
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return bb.createOperation(result);
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} else
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return oldOp;
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@ -319,3 +319,16 @@ func @use_value_of_external(%A: memref<16xf64, #tile>, %B: f64) -> (memref<8xf64
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}
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// CHECK: %[[res:[0-9]+]] = call @external_func_B(%[[A]], %[[B]]) : (memref<4x4xf64>, f64) -> memref<2x4xf64>
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// CHECK: return %{{.*}} : memref<2x4xf64>
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// CHECK-LABEL: func @affine_parallel_norm
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func @affine_parallel_norm() -> memref<8xf32, #tile> {
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%c = constant 23.0 : f32
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%a = alloc() : memref<8xf32, #tile>
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// CHECK: affine.parallel (%{{.*}}) = (0) to (8) reduce ("assign") -> (memref<2x4xf32>)
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%1 = affine.parallel (%i) = (0) to (8) reduce ("assign") -> memref<8xf32, #tile> {
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affine.store %c, %a[%i] : memref<8xf32, #tile>
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// CHECK: affine.yield %{{.*}} : memref<2x4xf32>
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affine.yield %a : memref<8xf32, #tile>
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}
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return %1 : memref<8xf32, #tile>
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}
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