forked from OSchip/llvm-project
[x86] Bring some sanity to the x86 CPU processor definitions.
Notably, this adds simple micro-architecture names for the Intel CPU variants, and defines the old 'core'-based names as aliases. GCC has started to simplify their documented interface to use these names as well, so it seems like we can start to converge on a consistent pattern. I'd appreciate Intel double checking the entries that aren't yet documented widely, especially Atom (Bonnell and Silvermont), Knights Landing, and Skylake. But this change shouldn't break any existing users. Also, ran clang-format to re-format this code and it actually worked (modulo a tiny bug) so hopefully we can start to stop thinking about formatting this stuff. llvm-svn: 223769
This commit is contained in:
Chandler Carruth
parent
72ccc3c428
commit
af892403c2
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@ -240,82 +240,155 @@ def : ProcessorModel<"core2", SandyBridgeModel,
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def : ProcessorModel<"penryn", SandyBridgeModel,
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[FeatureSSE41, FeatureCMPXCHG16B, FeatureSlowBTMem]>;
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// Atom.
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def : ProcessorModel<"atom", AtomModel,
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[ProcIntelAtom, FeatureSSSE3, FeatureCMPXCHG16B,
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FeatureMOVBE, FeatureSlowBTMem, FeatureLeaForSP,
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FeatureSlowDivide32, FeatureSlowDivide64,
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// Atom CPUs.
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class BonnellProc<string Name> : ProcessorModel<Name, AtomModel, [
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ProcIntelAtom,
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FeatureSSSE3,
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FeatureCMPXCHG16B,
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FeatureMOVBE,
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FeatureSlowBTMem,
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FeatureLeaForSP,
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FeatureSlowDivide32,
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FeatureSlowDivide64,
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FeatureCallRegIndirect,
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FeatureLEAUsesAG,
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FeaturePadShortFunctions]>;
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FeaturePadShortFunctions
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]>;
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def : BonnellProc<"bonnell">;
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def : BonnellProc<"atom">; // Pin the generic name to the baseline.
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// Atom Silvermont.
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def : ProcessorModel<"slm", SLMModel, [ProcIntelSLM,
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FeatureSSE42, FeatureCMPXCHG16B,
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FeatureMOVBE, FeaturePOPCNT,
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FeaturePCLMUL, FeatureAES,
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class SilvermontProc<string Name> : ProcessorModel<Name, SLMModel, [
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ProcIntelSLM,
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FeatureSSE42,
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FeatureCMPXCHG16B,
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FeatureMOVBE,
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FeaturePOPCNT,
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FeaturePCLMUL,
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FeatureAES,
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FeatureSlowDivide64,
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FeatureCallRegIndirect,
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FeaturePRFCHW,
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FeatureSlowLEA, FeatureSlowIncDec,
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FeatureSlowBTMem, FeatureFastUAMem]>;
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// "Arrandale" along with corei3 and corei5
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def : ProcessorModel<"corei7", SandyBridgeModel,
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[FeatureSSE42, FeatureCMPXCHG16B, FeatureSlowBTMem,
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FeatureFastUAMem, FeaturePOPCNT, FeatureAES]>;
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FeatureSlowLEA,
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FeatureSlowIncDec,
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FeatureSlowBTMem,
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FeatureFastUAMem
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]>;
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def : SilvermontProc<"silvermont">;
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def : SilvermontProc<"slm">; // Legacy alias.
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// "Arrandale" along with corei3 and corei5
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class NehalemProc<string Name, list<SubtargetFeature> AdditionalFeatures>
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: ProcessorModel<Name, SandyBridgeModel, !listconcat([
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FeatureSSE42,
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FeatureCMPXCHG16B,
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FeatureSlowBTMem,
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FeatureFastUAMem,
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FeaturePOPCNT
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],
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AdditionalFeatures)>;
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def : NehalemProc<"nehalem", []>;
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def : NehalemProc<"corei7", [FeatureAES]>;
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def : ProcessorModel<"nehalem", SandyBridgeModel,
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[FeatureSSE42, FeatureCMPXCHG16B, FeatureSlowBTMem,
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FeatureFastUAMem, FeaturePOPCNT]>;
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// Westmere is a similar machine to nehalem with some additional features.
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// Westmere is the corei3/i5/i7 path from nehalem to sandybridge
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def : ProcessorModel<"westmere", SandyBridgeModel,
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[FeatureSSE42, FeatureCMPXCHG16B, FeatureSlowBTMem,
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FeatureFastUAMem, FeaturePOPCNT, FeatureAES,
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FeaturePCLMUL]>;
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// Sandy Bridge
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class WestmereProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
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FeatureSSE42,
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FeatureCMPXCHG16B,
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FeatureSlowBTMem,
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FeatureFastUAMem,
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FeaturePOPCNT,
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FeatureAES,
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FeaturePCLMUL
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]>;
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def : WestmereProc<"westmere">;
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// SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
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// rather than a superset.
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def : ProcessorModel<"corei7-avx", SandyBridgeModel,
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[FeatureAVX, FeatureCMPXCHG16B, FeatureFastUAMem,
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FeatureSlowUAMem32, FeaturePOPCNT, FeatureAES,
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FeaturePCLMUL]>;
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// Ivy Bridge
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def : ProcessorModel<"core-avx-i", SandyBridgeModel,
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[FeatureAVX, FeatureCMPXCHG16B, FeatureFastUAMem,
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FeatureSlowUAMem32, FeaturePOPCNT, FeatureAES,
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FeaturePCLMUL, FeatureRDRAND, FeatureF16C,
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FeatureFSGSBase]>;
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class SandyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
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FeatureAVX,
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FeatureCMPXCHG16B,
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FeatureFastUAMem,
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FeatureSlowUAMem32,
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FeaturePOPCNT,
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FeatureAES,
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FeaturePCLMUL
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]>;
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def : SandyBridgeProc<"sandybridge">;
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def : SandyBridgeProc<"corei7-avx">; // Legacy alias.
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// Haswell
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def : ProcessorModel<"core-avx2", HaswellModel,
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[FeatureAVX2, FeatureCMPXCHG16B, FeatureFastUAMem,
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FeaturePOPCNT, FeatureAES, FeaturePCLMUL, FeatureRDRAND,
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FeatureF16C, FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT,
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FeatureBMI, FeatureBMI2, FeatureFMA, FeatureRTM,
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FeatureHLE, FeatureSlowIncDec]>;
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class IvyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
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FeatureAVX,
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FeatureCMPXCHG16B,
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FeatureFastUAMem,
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FeatureSlowUAMem32,
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FeaturePOPCNT,
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FeatureAES,
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FeaturePCLMUL,
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FeatureRDRAND,
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FeatureF16C,
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FeatureFSGSBase
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]>;
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def : IvyBridgeProc<"ivybridge">;
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def : IvyBridgeProc<"core-avx-i">; // Legacy alias.
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class HaswellProc<string Name> : ProcessorModel<Name, HaswellModel, [
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FeatureAVX2,
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FeatureCMPXCHG16B,
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FeatureFastUAMem,
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FeaturePOPCNT,
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FeatureAES,
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FeaturePCLMUL,
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FeatureRDRAND,
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FeatureF16C,
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FeatureFSGSBase,
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FeatureMOVBE,
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FeatureLZCNT,
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FeatureBMI,
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FeatureBMI2,
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FeatureFMA,
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FeatureRTM,
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FeatureHLE,
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FeatureSlowIncDec
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]>;
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def : HaswellProc<"haswell">;
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def : HaswellProc<"core-avx2">; // Legacy alias.
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class BroadwellProc<string Name> : ProcessorModel<Name, HaswellModel, [
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FeatureAVX2,
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FeatureCMPXCHG16B,
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FeatureFastUAMem,
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FeaturePOPCNT,
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FeatureAES,
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FeaturePCLMUL,
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FeatureRDRAND,
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FeatureF16C,
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FeatureFSGSBase,
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FeatureMOVBE,
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FeatureLZCNT,
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FeatureBMI,
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FeatureBMI2,
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FeatureFMA,
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FeatureRTM,
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FeatureHLE,
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FeatureADX,
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FeatureRDSEED,
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FeatureSMAP,
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FeatureSlowIncDec
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]>;
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def : BroadwellProc<"broadwell">;
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// Broadwell
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def : ProcessorModel<"broadwell", HaswellModel,
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[FeatureAVX2, FeatureCMPXCHG16B, FeatureFastUAMem,
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FeaturePOPCNT, FeatureAES, FeaturePCLMUL, FeatureRDRAND,
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FeatureF16C, FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT,
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FeatureBMI, FeatureBMI2, FeatureFMA, FeatureRTM,
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FeatureHLE, FeatureADX, FeatureRDSEED, FeatureSMAP,
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FeatureSlowIncDec]>;
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// KNL
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// FIXME: define KNL model
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def : ProcessorModel<"knl", HaswellModel,
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class KnightsLandingProc<string Name> : ProcessorModel<Name, HaswellModel,
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[FeatureAVX512, FeatureERI, FeatureCDI, FeaturePFI,
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FeatureCMPXCHG16B, FeatureFastUAMem, FeaturePOPCNT,
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FeatureAES, FeaturePCLMUL, FeatureRDRAND, FeatureF16C,
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FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT, FeatureBMI,
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FeatureBMI2, FeatureFMA, FeatureRTM, FeatureHLE,
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FeatureSlowIncDec]>;
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def : KnightsLandingProc<"knl">;
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// SKX
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// FIXME: define SKX model
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def : ProcessorModel<"skx", HaswellModel,
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class SkylakeProc<string Name> : ProcessorModel<Name, HaswellModel,
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[FeatureAVX512, FeatureCDI,
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FeatureDQI, FeatureBWI, FeatureVLX,
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FeatureCMPXCHG16B, FeatureFastUAMem, FeaturePOPCNT,
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@ -323,6 +396,11 @@ def : ProcessorModel<"skx", HaswellModel,
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FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT, FeatureBMI,
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FeatureBMI2, FeatureFMA, FeatureRTM, FeatureHLE,
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FeatureSlowIncDec, FeatureSGX]>;
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def : SkylakeProc<"skylake">;
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def : SkylakeProc<"skx">; // Legacy alias.
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// AMD CPUs.
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def : Proc<"k6", [FeatureMMX]>;
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def : Proc<"k6-2", [Feature3DNow]>;
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