From af73d2bdd923896303a7adef61d04f3e3813b56a Mon Sep 17 00:00:00 2001
From: Krzysztof Parzyszek <kparzysz@codeaurora.org>
Date: Fri, 4 May 2018 13:59:05 +0000
Subject: [PATCH] [Hexagon] Skip reserved physical registers when updating
 liveness

llvm-svn: 331518
---
 .../Target/Hexagon/HexagonExpandCondsets.cpp  |  9 +++++-
 .../Hexagon/expand-condsets-phys-reg.mir      | 30 +++++++++++++++++++
 2 files changed, 38 insertions(+), 1 deletion(-)
 create mode 100644 llvm/test/CodeGen/Hexagon/expand-condsets-phys-reg.mir

diff --git a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
index f46f6105c17f..06caa2feffab 100644
--- a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
@@ -547,7 +547,14 @@ void HexagonExpandCondsets::removeInstr(MachineInstr &MI) {
 void HexagonExpandCondsets::updateLiveness(std::set<unsigned> &RegSet,
       bool Recalc, bool UpdateKills, bool UpdateDeads) {
   UpdateKills |= UpdateDeads;
-  for (auto R : RegSet) {
+  for (unsigned R : RegSet) {
+    if (!TargetRegisterInfo::isVirtualRegister(R)) {
+      assert(TargetRegisterInfo::isPhysicalRegister(R));
+      // There shouldn't be any physical registers as operands, except
+      // possibly reserved registers.
+      assert(MRI->isReserved(R));
+      continue;
+    }
     if (Recalc)
       recalculateLiveInterval(R);
     if (UpdateKills)
diff --git a/llvm/test/CodeGen/Hexagon/expand-condsets-phys-reg.mir b/llvm/test/CodeGen/Hexagon/expand-condsets-phys-reg.mir
new file mode 100644
index 000000000000..2484f6b8fe68
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/expand-condsets-phys-reg.mir
@@ -0,0 +1,30 @@
+# RUN: llc -march=hexagon -run-pass expand-condsets %s -o - | FileCheck %s
+# REQUIRES: asserts
+
+# The physical register as an operand to C2_mux caused a crash.
+# Check that this compiles successfully and that the mux is expanded.
+
+# CHECK: %2:intregs = A2_tfrt %1, $r31
+# CHECK: %2:intregs = A2_tfrf killed %1, killed %0, implicit %2(tied-def 0)
+
+name: fred
+tracksRegLiveness: true
+body: |
+  bb.0:
+    successors: %bb.1, %bb.2
+    liveins: $r0
+
+    %0:intregs = A2_tfrsi 0           ;; Multiple defs to ensure IsSSA = false
+    %0:intregs = L2_loadri_io $r0, 0
+    %1:predregs = C2_cmplt %0, 10
+    %2:intregs = C2_mux %1, $r31, %0
+    %3:predregs = C2_cmpeqi %2, 0
+    J2_jumpt %3, %bb.1, implicit-def $pc
+    J2_jump %bb.2, implicit-def $pc
+
+  bb.1:
+    PS_jmpret $r31, implicit-def $pc
+
+  bb.2:
+    PS_jmpret $r31, implicit-def $pc
+...