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Remove incorrect pattern for ARM SMML instruction. 

Patch by Meador Inge.

llvm-svn: 156989
This commit is contained in:
Tim Northover 2012-05-17 13:12:13 +00:00
parent e1decdf68a
commit af501a29d3
2 changed files with 14 additions and 2 deletions
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3
llvm/lib/Target/ARM/ARMInstrInfo.td
View File

@ -3554,8 +3554,7 @@ def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
(ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra",
[(set GPR:$Rd, (sub GPR:$Ra, (mulhs GPR:$Rn, GPR:$Rm)))]>,
IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>,
Requires<[IsARM, HasV6]>;
def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),

13
llvm/test/CodeGen/ARM/smml.ll Normal file
View File

@ -0,0 +1,13 @@
; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s
define i32 @f(i32 %a, i32 %b, i32 %c) nounwind readnone ssp {
entry:
; CHECK-NOT: smmls
%conv4 = zext i32 %a to i64
%conv1 = sext i32 %b to i64
%conv2 = sext i32 %c to i64
%mul = mul nsw i64 %conv2, %conv1
%shr5 = lshr i64 %mul, 32
%sub = sub nsw i64 %conv4, %shr5
%conv3 = trunc i64 %sub to i32
ret i32 %conv3
}