forked from OSchip/llvm-project
[AArch64][GlobalISel] Fix atomic truncating stores from generating invalid copies.
If the source reg is a 64b vreg, then we need to emit a subreg copy to a 32b gpr before we select sub-64b variants like STLRW.
This commit is contained in:
Amara Emerson
parent
d71bb6a409
commit
af4dc633f8
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@ -2770,6 +2770,14 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
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} else {
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static unsigned Opcodes[] = {AArch64::STLRB, AArch64::STLRH,
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AArch64::STLRW, AArch64::STLRX};
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Register ValReg = LdSt.getReg(0);
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if (MRI.getType(ValReg).getSizeInBits() == 64 && MemSizeInBits != 64) {
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// Emit a subreg copy of 32 bits.
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Register NewVal = MRI.createVirtualRegister(&AArch64::GPR32RegClass);
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MIB.buildInstr(TargetOpcode::COPY, {NewVal}, {})
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.addReg(I.getOperand(0).getReg(), 0, AArch64::sub_32);
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I.getOperand(0).setReg(NewVal);
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}
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I.setDesc(TII.get(Opcodes[Log2_32(MemSizeInBytes)]));
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}
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constrainSelectedInstRegOperands(I, TII, TRI, RBI);
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@ -0,0 +1,150 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=1 %s -o - | FileCheck %s
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---
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name: truncstore_atomic_32
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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liveins:
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- { reg: '$x0' }
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- { reg: '$w1' }
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body: |
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; CHECK-LABEL: name: truncstore_atomic_32
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
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; CHECK-NEXT: liveins: $w1, $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
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; CHECK-NEXT: TBNZW [[COPY1]], 0, %bb.2
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; CHECK-NEXT: B %bb.1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: successors: %bb.2(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 4
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; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY [[SUBREG_TO_REG]].sub_32
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; CHECK-NEXT: STLRW [[COPY2]], [[COPY]] :: (store release (s32))
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: RET_ReallyLR
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bb.1:
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liveins: $w1, $x0
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%0:gpr(p0) = COPY $x0
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%3:gpr(s32) = COPY $w1
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%2:gpr(s8) = G_TRUNC %3(s32)
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%4:gpr(s8) = G_ASSERT_ZEXT %2, 1
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%1:gpr(s1) = G_TRUNC %4(s8)
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G_BRCOND %1(s1), %bb.3
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G_BR %bb.2
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bb.2:
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%8:gpr(s64) = G_CONSTANT i64 4
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G_STORE %8(s64), %0(p0) :: (store release (s32))
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bb.3:
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RET_ReallyLR
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...
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---
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name: truncstore_atomic_16
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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liveins:
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- { reg: '$x0' }
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- { reg: '$w1' }
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body: |
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; CHECK-LABEL: name: truncstore_atomic_16
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
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; CHECK-NEXT: liveins: $w1, $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
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; CHECK-NEXT: TBNZW [[COPY1]], 0, %bb.2
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; CHECK-NEXT: B %bb.1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: successors: %bb.2(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 4
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; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY [[SUBREG_TO_REG]].sub_32
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; CHECK-NEXT: STLRH [[COPY2]], [[COPY]] :: (store release (s16))
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: RET_ReallyLR
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bb.1:
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liveins: $w1, $x0
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%0:gpr(p0) = COPY $x0
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%3:gpr(s32) = COPY $w1
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%2:gpr(s8) = G_TRUNC %3(s32)
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%4:gpr(s8) = G_ASSERT_ZEXT %2, 1
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%1:gpr(s1) = G_TRUNC %4(s8)
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G_BRCOND %1(s1), %bb.3
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G_BR %bb.2
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bb.2:
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%8:gpr(s64) = G_CONSTANT i64 4
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G_STORE %8(s64), %0(p0) :: (store release (s16))
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bb.3:
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RET_ReallyLR
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...
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---
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name: truncstore_atomic_8
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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liveins:
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- { reg: '$x0' }
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- { reg: '$w1' }
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body: |
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; CHECK-LABEL: name: truncstore_atomic_8
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
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; CHECK-NEXT: liveins: $w1, $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
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; CHECK-NEXT: TBNZW [[COPY1]], 0, %bb.2
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; CHECK-NEXT: B %bb.1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: successors: %bb.2(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 4
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; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY [[SUBREG_TO_REG]].sub_32
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; CHECK-NEXT: STLRB [[COPY2]], [[COPY]] :: (store release (s8))
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: RET_ReallyLR
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bb.1:
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liveins: $w1, $x0
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%0:gpr(p0) = COPY $x0
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%3:gpr(s32) = COPY $w1
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%2:gpr(s8) = G_TRUNC %3(s32)
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%4:gpr(s8) = G_ASSERT_ZEXT %2, 1
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%1:gpr(s1) = G_TRUNC %4(s8)
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G_BRCOND %1(s1), %bb.3
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G_BR %bb.2
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bb.2:
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%8:gpr(s64) = G_CONSTANT i64 4
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G_STORE %8(s64), %0(p0) :: (store release (s8))
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bb.3:
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RET_ReallyLR
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...
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