maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

[X86][tests] Added rotate_vec.ll CodeGen test. NFC precommit for bug 33691 fix. 

llvm-svn: 307937
This commit is contained in:
Andrew Zhogin 2017-07-13 18:57:40 +00:00
parent 3064fae5a6
commit af3d5fe83b
1 changed files with 60 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

60
llvm/test/CodeGen/X86/rotate_vec.ll Normal file
View File

@ -0,0 +1,60 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=bdver4 | FileCheck %s
define <4 x i32> @rot_v4i32_splat(<4 x i32> %x) {
; CHECK-LABEL: rot_v4i32_splat:
; CHECK: # BB#0:
; CHECK-NEXT: vprotd $31, %xmm0, %xmm0
; CHECK-NEXT: retq
%1 = lshr <4 x i32> %x, <i32 1, i32 1, i32 1, i32 1>
%2 = shl <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>
%3 = or <4 x i32> %1, %2
ret <4 x i32> %3
}
define <4 x i32> @rot_v4i32_non_splat(<4 x i32> %x) {
; CHECK-LABEL: rot_v4i32_non_splat:
; CHECK: # BB#0:
; CHECK-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm1
; CHECK-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
; CHECK-NEXT: vpor %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq
%1 = lshr <4 x i32> %x, <i32 1, i32 2, i32 3, i32 4>
%2 = shl <4 x i32> %x, <i32 31, i32 30, i32 29, i32 28>
%3 = or <4 x i32> %1, %2
ret <4 x i32> %3
}
define <4 x i32> @rot_v4i32_splat_2masks(<4 x i32> %x) {
; CHECK-LABEL: rot_v4i32_splat_2masks:
; CHECK: # BB#0:
; CHECK-NEXT: vprotd $31, %xmm0, %xmm0
; CHECK-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; CHECK-NEXT: retq
%1 = lshr <4 x i32> %x, <i32 1, i32 1, i32 1, i32 1>
%2 = and <4 x i32> %1, <i32 4294901760, i32 4294901760, i32 4294901760, i32 4294901760>
%3 = shl <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>
%4 = and <4 x i32> %3, <i32 0, i32 4294901760, i32 0, i32 4294901760>
%5 = or <4 x i32> %2, %4
ret <4 x i32> %5
}
define <4 x i32> @rot_v4i32_non_splat_2masks(<4 x i32> %x) {
; CHECK-LABEL: rot_v4i32_non_splat_2masks:
; CHECK: # BB#0:
; CHECK-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm1
; CHECK-NEXT: vpxor %xmm2, %xmm2, %xmm2
; CHECK-NEXT: vpblendw {{.*#+}} xmm1 = xmm2[0],xmm1[1],xmm2[2],xmm1[3],xmm2[4],xmm1[5],xmm2[6],xmm1[7]
; CHECK-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
; CHECK-NEXT: vpblendw {{.*#+}} xmm0 = xmm2[0,1,2],xmm0[3],xmm2[4,5,6],xmm0[7]
; CHECK-NEXT: vpor %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq
%1 = lshr <4 x i32> %x, <i32 1, i32 2, i32 3, i32 4>
%2 = and <4 x i32> %1, <i32 4294901760, i32 4294901760, i32 4294901760, i32 4294901760>
%3 = shl <4 x i32> %x, <i32 31, i32 30, i32 29, i32 28>
%4 = and <4 x i32> %3, <i32 0, i32 4294901760, i32 0, i32 4294901760>
%5 = or <4 x i32> %2, %4
ret <4 x i32> %5
}